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參數(shù)資料
| 型號： | SME5410MCZ-270 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 270 MHz, RISC PROCESSOR, XMA |
| 封裝： | 130 X 100 MM, 45 MM HEIGHT MODULE |
| 文件頁數(shù)： | 9/30頁 |
| 文件大?。?/td> | 183K |
| 代理商： | SME5410MCZ-270 |
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270 MHz CPU, 256 Kbyte E-cache, UPA, 66 MHz PCI
UltraSPARC-IIi CPU Module
SME5410MCZ-270
July 1998
Sun Microsystems, Inc
UPA
Within the module design, the following sets of clock signals are synchronous:
UltraSPARC-IIi SRAM_CLK
UltraSPARC-IIi UPA_CLK
UPA_CLK input to the fast-frame-buffer ASIC external to the module
CPU_CLK input to the UltraSPARC-IIi processor
Any timing mismatches between these clocks linearly degrade the timing to and from the UltraSPARC-IIi
and fast frame buffer (FFB). The FFB uses the UPA64S data interface.
Since these signals are completely contained on the module (with the exception of the UPA_CLK), the system
board must match the delay assumed by the module design.
The clock skew includes:
Separate buffers on the module:
± 200 ps
UltraSPARC-IIi and FFB sockets:
± 50 ps.
Board fabrication variance:
± 250 ps
Setup/hold/clock input to data-output delay differences:
± 150 ps
System noise:
± 150 ps
When doing a system timing budget, this total skew must be added to the setup, hold, and propagation times
listed for UPA and DRAM signals in the CPU component data sheet (SME1040).
The module is designed for 6 inches of motherboard trace plus 3.4 in of FFB trace plus simulated differences
in ASIC/UltraSPARC-IIi setup times. These are internal
≈ 180 ps/inch. traces.
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