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參數(shù)資料
| 型號： | SME5410MCZ-270 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 270 MHz, RISC PROCESSOR, XMA |
| 封裝： | 130 X 100 MM, 45 MM HEIGHT MODULE |
| 文件頁數(shù)： | 8/30頁 |
| 文件大小： | 183K |
| 代理商： | SME5410MCZ-270 |
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SME5410MCZ-270
270 MHz CPU, 256 Kbyte E-cache, UPA, 66 MHz PCI
UltraSPARC-IIi CPU Module
July 1998
Sun Microsystems, Inc
TIMING SPECIFICATIONS
Timing design within the module makes demands upon signal timing at the module connectors. This section
describes internal module timing when it is useful to explain external requirements. For detailed information
on timing and latencies see Sun publications:
UltraSPARC–IIi Microprocessor Data Sheet, SME1040CGA [1]
UltraSPARC–IIi Microprocessor User’s Manual, SME1040CGA [2]
PCI
PCI_CLK and PCI_REF_CLK traces on the module are matched in length to within 0.5 in, that is, about 100 ps
at a nominal length of 550 ps. These signals have no added delay and their trace lengths are also within
± 0.5
in of those of the other PCI signals. Setup, hold and propagation times are listed in the UltraSPARC-IIi pro-
cessor component data sheet [1].
DRAM
DRAM signals are all matched to within 0.5 inches on the module.
SRAM
The UltraSPARC-IIi processor’s second level (L2) cache is implemented using synchronous SRAMs
mounted on the module. The data bus is 64 bits plus 8 parity bits. There is also a tag SRAM interfacing to a
16-bit bus that includes two parity bits. While the tag and data SRAMs share no signals, the tag implements
the same timing scheme as the data SRAMs for a given module. Generally the tag SRAM timing is slightly
less critical than for the data SRAMs. This is due to two factors: one, the physical layout of the data bits and
address bits; and two, the additional loading on the data SRAM interface.
1.
Document Part Number: 805-0086-03
2.
Document Part Number: 805-0087-01
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