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參數(shù)資料
| 型號(hào)： | SME5410MCZ-270 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 270 MHz, RISC PROCESSOR, XMA |
| 封裝： | 130 X 100 MM, 45 MM HEIGHT MODULE |
| 文件頁數(shù)： | 23/30頁 |
| 文件大?。?/td> | 183K |
| 代理商： | SME5410MCZ-270 |
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270 MHz CPU, 256 Kbyte E-cache, UPA, 66 MHz PCI
UltraSPARC-IIi CPU Module
SME5410MCZ-270
July 1998
Sun Microsystems, Inc
UltraSPARC-IIi CPU
The UltraSPARC-IIi processor is a high-performance, highly integrated, superscalar processor implement-
ing the SPARC V9 64-bit RISC architecture. It is capable of sustaining the execution of up to four instructions
per cycle even in the presence of conditional branches and cache misses. It supports a 44-bit virtual address
space and a 41-bit physical address space. The instruction set also includes the Visual Instruction Set (VIS)
that accommodates the following functions:
the most common operations related to two-dimensional image processing
three-dimensional graphics
video compression and decompression algorithms and other pixel-based algorithms
support for high-bandwidth bcopy through block load and block store instructions
The UltraSPARC-IIi CPU is packaged in a ceramic 587-pin 1.27 mm Land Grid Array (LGA) package. The
package dimension is 37.5 mm by 37.5 mm.
The PCI interface supports the PCI 2.1 specication with a 66 MHz clock rate or 33 MHz across a PCI bridge,
for example the Advanced PCI Bridge (APB). PCI DMA transfers are cache coherent.
External Cache
The 0.5Mbyte external cache is connected to the E-cache data bus and is implemented in ve synchronous
register-latch SRAM ICs:
four 64K x 18 data SRAMs congured as 64K x 64-bit data + 8-bit byte parity
one 64K x 18 tag SRAM
The CPU-SRAM interface runs at half of the CPU pipeline frequency. SRAM signals operate at 2.6V LVCMOS
levels. The SRAM clock is a differential low-voltage PECL input.
The external cache SRAMs operate in “2–2” (Register-Latched) mode which means that it takes two processor
clocks to send the address and two clocks to access and return the E-cache data. 2–2 mode has a four cycle
pin-to-pin latency, which provides lower E-cache latency. In addition, no dead cycles are necessary when
alternating between reads and writes because of tighter control over turn on and turn off times in these
SRAMs.
The cache SRAMs are plastic 119-pin, 50-mil BGA packages measuring 22 mm by 14 mm.
System Functions
System clock division is arranged to clock the on-board subsystems at the following frequencies (relative to
internal CPU clock):
UPA system interface: 64-bit, operating at 1/3 CPU frequency
PCI bus: 32-bit, runs at 66 MHz (maximum)
On-module E-cache SRAM: 64 bit, runs at 1/2 CPU frequency
DRAM interface: congured for external multiplexing to 128 bits + 16 ECC bits at the DRAM
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