參數(shù)資料
型號(hào): SME5410MCZ-270
元件分類: 微控制器/微處理器
英文描述: 64-BIT, 270 MHz, RISC PROCESSOR, XMA
封裝: 130 X 100 MM, 45 MM HEIGHT MODULE
文件頁(yè)數(shù): 28/30頁(yè)
文件大?。?/td> 183K
代理商: SME5410MCZ-270
7
270 MHz CPU, 256 Kbyte E-cache, UPA, 66 MHz PCI
UltraSPARC-IIi CPU Module
SME5410MCZ-270
July 1998
Sun Microsystems, Inc
All sustained DMA numbers are for a single device. Multiple devices on separate secondary buses can cause
higher sustained bandwidths. In no case is the combined bandwidth from two secondary buses less than the
peak bandwidth available from one bus. This is because of efcient internal arbitration between multiple
events in the bus bridge.
PCI Bandwidth
PCI Sustained Bandwidth
To DRAM from Processor
PCI Bus (DMA)
66 MHz, 32-bit
Random 64-byte reads
132 Mbyte/s
Random 64-byte writes
151 Mbyte/s
To E-cache from
Processor PCI Bus (DMA)
66 MHz, 32-bit
Random 64-byte reads
163 Mbyte/s
Random 64-byte writes
186 Mbyte/s
From Processor to
Processor PCI bus (PIO)
66 MHz, 32-bit
64-byte writes
200 Mbyte/s
UPA64S Bandwidth
UPA PIO Bandwidth
From Processor, to
UPA64S (PIO)
90 MHz, 64-bit
Random 64-byte writes
540 Mbyte/s
Compressed 8-byte writes
720 Mbyte/s
PCI Bandwidth with APB (33MHz Secondary Bus)
PCI Secondary Sustained Bandwidth
From Processor, to
Secondary PCI Bus (PIO)
33 MHz, 32-bit
64-byte Writes
124 Mbyte/s
To DRAM from Secondary
PCI Bus (DMA)
33 MHz, 32-bit
Random 64-byte reads
78 Mbyte/s
Random 64-byte writes
124 Mbyte/s
相關(guān)PDF資料
PDF描述
SME5434PCI-440 64-BIT, 440 MHz, RISC PROCESSOR, XMA
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