參數(shù)資料
型號(hào)： SII3114CT176
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PQFP176
封裝： TQFP-176
文件頁數(shù)： 123/127頁
文件大小： 564K
代理商： SII3114CT176
SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2007 Silicon Image, Inc.
87
SiI-DS-0103-D
Table 31 shows the default configurations of all Serial ATA FIS types.
Table 31. Default FIS Configurations
Configuration Bits
FIS
Code
FIS Name
Register Bits
Default Value
Comments
27h
Register (Host to Device)
FIS27cfg[1:0]
01b
Default to reject FIS without interlock.
34h
Register (Device to Host)
FIS34cfg[1:0]
00b
Default to accept FIS without interlock.
39h
DMA Activate
FIS39cfg[1:0]
00b
Default to accept FIS without interlock.
41h
DMA Setup
FIS41cfg[1:0]
01b
Default to reject.
46h
Data
FIS46cfg[1:0]
00b
Default to accept FIS without interlock.
58h
BIST Activate
FIS58cfg[1:0]
00b
Default to accept for far-end retimed loopback,
reject for any other.
5Fh
PIO Setup
FIS5Fcfg[1:0]
00b
Default to accept FIS without interlock.
A1h
Set Device Bits
FISa1cfg[1:0]
00b
Default to accept FIS without interlock.
A6h
reserved
FISa6cfg[1:0]
01b
Default to reject FIS without interlock.
B8h
reserved
FISb8cfg[1:0]
01b
Default to reject FIS without interlock.
BFh
reserved
FISbFcfg[1:0]
01b
Default to reject FIS without interlock.
C7h
reserved
FISc7cfg[1:0]
01b
Default to reject FIS without interlock.
D4h
reserved
FISd4cfg[1:0]
01b
Default to reject FIS without interlock.
D9h
reserved
FISd9cfg[1:0]
01b
Default to reject FIS without interlock.
Others reserved
FISocfg[1:0]
01b
Default to reject FIS without interlock.
RxFIS[0-6]- First seven dwords received from device. RxFIS[0] is the first dword that contains the FIS header.
RxFIS[6] is the last of the seven dwords received. It is enough to support DMA Setup FIS.
Note that:
FIS data can also be read out directly from RxFIS (first seven dwords).
All data to be transferred must be sent within one UDMA burst. Burst termination will not be allowed and
may produce unpredictable result.
There is no limit on received frame size.
In a Data FIS, the receive FIFO will automatically advance one dword to skip the header. Upon an
interlocked FIS, the FIFO read pointer will rewind to the beginning so that the first dword read is the
header.
The following summarizes the behavior:
On power up, the default configurations are as follows:
All defined FISes, except BIST Activate and DMA Setup, default to be supported (FISxxcfg[1:0] = '00').
BIST Activate is default to be accepted ONLY for Far-end Retimed Loopback and to be rejected for any
other BIST types.
DMA Setup defaults to be rejected.
All undefined FISes default to be rejected (FISxxcfg[1:0] = '01').
Sequences:
Upon reception of an unsupported FIS (FISxxcfg[1:0] = '01'), the Link/Transport Logic responds with
R_ERR to the downstream device. The host will not be notified.
Upon reception of a supported FIS (FISxxcfg[1:0] = '00'), the Link/Transport Logic responds with
R_OK at WTRM (if no error is detected) or R_ERR (if an error is detected) to the downstream device.
The host will be notified only as required by the protocol.
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