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| 型號(hào)： | SII3114CT176 |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP176 |
| 封裝： | TQFP-176 |
| 文件頁(yè)數(shù)： | 122/127頁(yè) |
| 文件大?。?/td> | 564K |
| 代理商： | SII3114CT176 |
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SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
SiI-DS-0103-D
86
2007 Silicon Image, Inc.
FIS Transmission
There are two ways in which a FIS transmission is initiated:
1.
Protocol-initiated FIS transmission, e.g., when an ATA command is written to the SiI3114 it will send a
Command Register FIS and expects some FIS(es) (e.g., PIO Setup, Register, DMA Activate, Data, Set
Device Bits).
2.
Transparent FIS transmission. The sequence is as follows:
Host sets the Transmit_FIS bit in the Smisc register (bit 30). This tells the Transport/Link logic that a
transparent FIS needs to be transmitted.
The Transport/Link logic responds by setting itself up to transfer data from the host through UMDA
cycles.
The host writes the data through the PCI interface. Note that the FIS header (Dword 0 that contains
the FIS type) must also be written. The Transport/Link logic sends the FIS to the device. Note that:
There is no size limit on a transparent FIS. Data written to the SiI3114 from setting of Transmit_FIS to
setting of FIS_Done (see below) will be transmitted in a FIS.
There must be an even number of words.
As in Data FIS, upon a transmission error, no retries can be supported. The PCI block must restart
the transparent FIS transmission from the beginning.
Serial ATA CRC is calculated by the Transport/Link logic. The host will NOT append the CRC at the
end.
After the last write, the host sets the FIS_Done bit in the Smisc register (bit 31). This indicates to the
link that all data for this transaction has been transferred. The Transport/Link logic will then close out
the FIS by appending CRC and EOF and wait for termination. If R_OK is received from the
downstream device, the Transmit_OK bit will be set to indicate to the host that the FIS has been
successfully transferred to the device. If there is an error in the transmission process (e.g., the FIS
not recognized by the downstream device) resulting in the device acknowledging the FIS with an
R_ERR, the F bit of the Serror Register will be set (Bit 25).
The values of the status registers are latched and will not be cleared automatically. Before the next
Transparent FIS is being sent, the host must clear the status bits by performing a write to the
particular status registers.
FIS Reception
The SiI3114 is capable of receiving Unrecognized FIS types through an Interlocked FIS scheme. This capability is
over and above the regular protocol related FISes as defined in the Serial ATA specifications.
In general, an internal table determines the behavior when receiving all possible FIS types. This table is defined in
the register SFISCfg. The configuration codes in the SFISCfg register is defined in Table 30.
Table 30. Configuration Bits for FIS Reception
FISxxCFG[1:0]
Comments
00b
Accept FIS without interlock. If there is no error detected for the entire FIS, R_OK will be sent after
EOF is received. If any error is received, R_ERR will be sent after EOF
01b
Reject FIS without interlock. R_ERR will be sent
10b
Interlock. This allows the host to examine the first dwords of the FIS to determine whether to accept or
reject the FIS
11b
Reserved.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SII3114CTU | 制造商:Silicon Image Inc 功能描述:PCI to Serial ATA Controller 176-Pin TQFP 制造商:SILICON 功能描述: |
| SII3124A | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI-X to Serial ATA Controller |
| SII3124ACBHU | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI-X to Serial ATA Controller |
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| SII3132CNU | 制造商:Silicon Image Inc 功能描述:PCI Express to Serial ATA Controller 88-Pin QFN |
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