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參數(shù)資料
| 型號： | SI5350C-AXXXXX-GU |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 133 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO24 |
| 封裝： | MO-137C, QSOP-24 |
| 文件頁數(shù)： | 4/22頁 |
| 文件大?。?/td> | 244K |
| 代理商： | SI5350C-AXXXXX-GU |
Si5350C
12
Rev. 0.2
Figure 5. Example of Generating Two Clock Frequencies from the Same Clock Output
Up to two frequency select pins are available on the Si5350C. Each of the frequency select pins can be linked to
any of the clock outputs as shown in Figure 6. For example, FS_0 can be linked to control clock frequency
selection on CLK0, CLK3, and CLK5; FS_1 can be used to control clock frequency selection on CLK1, CLK2, and
CLK4. Any other combination is also possible.
The Si5350C uses control circuitry to ensure that frequency changes are glitchless. This ensures that the clock
always completes its last cycle before starting a new clock cycle of a different frequency.
Figure 6. Example Configuration of a Pin-Controlled Frequency Select (FS)
4.4.3. Output Enable (OEB_0, OEB_1, OEB_2)
Up to three output enable pins (OEB_0/1/2) are available on the Si5350C. Similar to the FS pins, each OEB pin
can be linked to any of the output clocks. In the example shown in Figure 7, OEB_0 is linked to control CLK0,
CLK3, and CLK5; OEB_1 is linked to control CLK6 and CLK7, and OEB_2 is linked to control CLK1, CLK2, CLK4,
and CLK5. Any other combination is also possible. If more than one OEB pin is linked to the same CLK output, the
pin forcing a disable state will be dominant. Clock outputs are enabled when the OEB pin is held low.
The output enable control circuitry ensures glitchless operation by starting the output clock cycle on the first leading
edge after OEB is asserted (OEB = low). When OEB is released (OEB = high), the clock is allowed to complete its
full clock cycle before going into a disabled state. This is shown in Figure 7. When disabled, the output state is
configurable as disabled high, disabled low, or disabled in high-impedance.
74.25 MHz or
74.25
1.001
MHz
27 MHz
XA
XB
CLK0
FS0
Si5350C
Free-running Clock
FS1
CLKIN
24.576 MHz or 22.5792 MHz
CLK1
Synchronous Clock
Video/Audio
Processor
Free-running Frequency
FS0
Bit Level
0
1
74.25 MHz
F1_0:
F2_0:
74.25
1.001
MHz
Synchronous Frequency
FS1
Bit Level
0
1
24.576 MHz
F1_1:
F2_1:
22.5792 MHz
54MHz
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
FS_0
FS_1
FS_0
0
1
F1_0, F1_3, F1_5
F2_0, F2_3, F2_5
Output Frequency
FS_1
0
1
F1_1, F1_2, F1_4
Output Frequency
CLKx
Frequency_A
Frequency_B
Full cycle completes before
changing to a new frequency
Frequency_A
New frequency starts
at its leading edge
Glitchless Frequency Changes
Cannot be controlled
by FS pins
Customizable FS Control
F2_1, F2_2, F2_4
MultiSynth 0
FS
MultiSynth 1
FS
MultiSynth 2
FS
MultiSynth 3
FS
MultiSynth 4
FS
MultiSynth 5
FS
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