參數(shù)資料
型號(hào)： SI5350C-AXXXXX-GU
廠商： SILICON LABORATORIES
元件分類(lèi)： 時(shí)鐘產(chǎn)生/分配
英文描述： 133 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO24
封裝： MO-137C, QSOP-24
文件頁(yè)數(shù)： 3/22頁(yè)
文件大?。?/td> 244K
代理商： SI5350C-AXXXXX-GU
Si5350C
Rev. 0.2
11
between system performance and EMI compliance. The amount of spread is configurable within the following
parameters:
Down spread: –0.5 to –2.5% modulation amplitude
An optional spread spectrum enable pin (SSEN) is configurable to enable or disable the spread spectrum feature.
Figure 4. Available Spread Spectrum Profiles
4.3.3. Invert/Non-Invert
By default, each of the output clocks are generated in phase (non-inverted) with respect to each other. An option to
invert any of the clock outputs is also available.
4.3.4. Output State When Disabled
There are up to three output enable pins configurable on the Si5350C as described in “4.4.5. Loss Of Lock (LOL)” .
The output state when disabled for each of the outputs is configurable as one of the following: disable low, disable
high, or disable in high-impedance.
4.3.5. Powering Down Unused Outputs
Unused clock outputs can be completely powered down to conserve power.
4.4. Programmable Control Pins (P0–P3) Options
Up to four programmable control pins (P0-P3) are configurable allowing direct pin control of the following features:
4.4.1. Spread Spectrum Enable (SSEN)
An optional control pin allows disabling the spread spectrum feature for all outputs that were configured with
spread spectrum enabled. Hold SSEN low to disable spread spectrum. The SSEN pin provides a convenient
method of evaluating the effect of using spread spectrum clocks during EMI compliance testing.
4.4.2. Frequency Select (FS_0, FS_1)
The Si5350C offers the option of configuring up to two frequencies per clock output (CLK0-CLK5) for either free-
running or synchronous clocks. This is a useful feature for applications that need to support more than one free-
running or synchronous clock rate on the same output. An example of this is shown in Figure 5. The FS pins select
which frequency is generated from the clock output. In this example FS0 select the output frequency on CLK0, and
FS1 selects the frequency on CLK1.
fc
R educed
A m plitude
and E M I
Do w n S p read
S pread A m ount
- 0.5% to - 2.5 %
fc
No S p read
Spectrum
C enter
F requency
A m plitude
相關(guān)PDF資料
PDF描述
SI5356AAXXXXXGM 200 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC24
SI5356A-AXXXXX-GMR 200 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC24
SI5369B-C-GQR 808 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP100
SI5369B-C-GQ 808 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP100
SI5369C-C-GQ 346 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP100
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SI5350C-B02166-GT 制造商:Silicon Laboratories Inc 功能描述:ANY-RATE, DUAL PLL 125MHZ CLOCK WITH DUAL INPUT, 3 OUTPUTS, - Rail/Tube
SI5350C-B02516-GT 制造商:Silicon Laboratories Inc 功能描述:ANY-RATE, DUAL PLL 160MHZ CLOCK WITH DUAL INPUT, 3 OUTPUTS, - Rail/Tube
SI5350C-B02569-GT 制造商:Silicon Laboratories Inc 功能描述:CONFIGURABLE CLOCK GENERATOR - Rail/Tube
SI5350C-B02570-GT 制造商:Silicon Laboratories Inc 功能描述:CONFIGURABLE CLOCK GENERATOR - Rail/Tube
Si5350C-Bxxxxx-GM 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Any-Rate, Dual PLL 160 MHz Clock with Dual Input, 8 outputs with 50? output impedance, 20-QFN (customized) RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
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