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參數(shù)資料
| 型號： | SI5023-D-GM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 5/28頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK/DATA RECVRY W/AMP 28MLP |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | DSPLL® |
| 類型： | 時鐘和數(shù)據(jù)恢復(fù)（CDR） |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，ATM 應(yīng)用 |
| 輸入： | 時鐘 |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.7GHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 28-QFN（5x5） |
| 包裝： | 管件 |
| 其它名稱： | 336-1276 |
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Si5023
Rev. 1.3
13
4.5. Operation With an External Reference
The Si5023 device’s optional external reference clock
centers the DSPLL, minimizes the acquisition time, and
maintains a stable output clock (CLKOUT) when lock-
to-reference (LTR) is asserted.
When the reference clock is present, the Si5023 will use
the reference clock to center the VCO output frequency
so that clock and data can be recovered from the input
data stream. The device will self configure for operation
with one of three reference clock frequencies. This
eliminates the need to externally configure the device to
operate with a particular reference clock.
The reference clock centers the VCO for a nominal
output between 2.5 and 2.7 GHz. The VCO frequency is
centered at 16, 32, or 128 times the reference clock
frequency. Detection circuitry continuously monitors the
reference clock input to determine whether the device
should be configured for a reference clock that is 1/16,
1/32, or 1/128 the nominal VCO output. Approximate
reference clock frequencies for some target applications
are given in Table 8.
4.6. Lock Detect
The Si5023 provides lock-detect circuitry that indicates
whether the PLL has achieved frequency lock with the
incoming data. The operation of the lock-detector
depends on the reference clock option used.
When an external reference clock is provided, the circuit
compares the frequency of a divided-down version of
the recovered clock with the frequency of the applied
reference clock (REFCLK). If the recovered clock
frequency deviates from that of the reference clock by
the amount specified in Table 4 on page 9, the PLL is
declared out of lock, and the loss-of-lock (LOL) pin is
asserted. In this state, the PLL will periodically try to
reacquire lock with the incoming data stream. During
reacquisition, the recovered clock frequency (CLKOUT)
drifts over a ±600 ppm range relative to the applied
reference clock, and the LOL output alarm may toggle
until the PLL has reacquired frequency lock. Due to the
low noise and stability of the DSPLL, there is the
possibility that the PLL will not drift enough to render an
out-of-lock condition, even if the data is removed from
inputs.
In applications requiring a more stable output clock
during out-of-lock conditions, the lock-to-reference
(LTR) input can be used to force the PLL to lock to the
externally supplied reference.
In the absence of an external reference, the lock detect
circuitry uses a data quality measure to determine when
frequency lock has been lost with the incoming data
stream. During reacquisition, CLKOUT may vary by
approximately ±10% from the nominal data rate.
4.7. Lock-to-Reference
The lock-to-reference input (LTR) can be used to force a
stable output clock when an alarm condition, such as
LOS, exists. In typical applications, the LOS output
would be tied to the LTR input to force a stable output
clock when the input data signal is lost. When LTR is
asserted, the DSPLL is prevented from acquiring the
data signal present on DIN. The operation of the LTR
control input depends on which reference clocking
mode is used.
When an external reference clock is present, assertion
of LTR will force the DSPLL to lock CLKOUT to the
provided reference. If no external reference clock is
used, LTR will force the DSPLL to hold the digital
frequency control input to the VCO at the last value.
This produces an output clock that is stable as long as
supply and temperature are constant.
4.8. Loss-of-Signal (LOS)
The Si5023 indicates a loss-of-signal condition on the
LOS output pin when the input peak-to-peak signal level
on DIN falls below an externally-controlled threshold.
The LOS threshold range is specified in Table 3 on
page 8 and is set by applying a voltage on the LOS_LVL
pin. The graph shown in Figure 6 illustrates the
LOS_LVL mapping to the LOS threshold. The LOS
output is asserted when the input signal drops below the
programmed peak-to-peak value. If desired, the LOS
function may be disabled by grounding LOS_LVL or by
adjusting LOS_LVL to be less than 1 V.
Note: The LOS circuit is designed to only work with pseudo-
random, dc-balanced data.
In many applications, it is desirable to produce a fixed
amount of signal hysteresis for an alarm indicator, such
as LOS, since a marginal data input signal could cause
intermittent toggling, leading to false alarm status.
When it is anticipated that very low-level DIN signals will
be encountered, the introduction of an adequate
amount of LOS hysteresis is recommended to minimize
any undesirable LOS signal toggling. Figure 7 illustrates
a simple circuit that may be used to set a fixed level of
Table 8. Typical REFCLK Frequencies
SONET/SDH
Gigabit
Ethernet
SONET/
SDH with
15/14 FEC
Ratio of
VCO to
REFCLK
19.44 MHz
19.53 MHz
20.83 MHz
128
77.76 MHz
78.125 MHz
83.31 MHz
32
155.52 MHz 156.25 MHz
16
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