參數(shù)資料
型號(hào)： SI5023-D-GM
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 4/28頁(yè)
文件大小： 0K
描述： IC CLOCK/DATA RECVRY W/AMP 28MLP
標(biāo)準(zhǔn)包裝： 60
系列： DSPLL®
類型： 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR）
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，ATM 應(yīng)用
輸入： 時(shí)鐘
輸出： CML
電路數(shù)： 1
比率 - 輸入:輸出： 1:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 2.7GHz
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 28-QFN（5x5）
包裝： 管件
其它名稱： 336-1276
Si5023
12
Rev. 1.3
4. Functional Description
The Si5023 integrates a high-speed limiting amplifier
(LA) with a multi-rate clock and data recovery unit
(CDR) that operates up to 2.7 Gbps. No external
reference clock is required for clock and data recovery.
The limiting amplifier magnifies low-level input data
signals from a TIA so that accurate clock and data
recovery can be performed. The CDR uses Silicon
Laboratories DSPLL technology to recover a clock
synchronous to the input data stream. The recovered
clock is used to retime the incoming data, and both are
output synchronously via current-mode logic (CML)
drivers.
Silicon
Laboratories’
DSPLL
technology
ensures superior jitter performance while eliminating the
need for external loop filter components found in
traditional phase-locked loop (PLL) implementations.
The limiting amplifier includes a control input for
adjusting the data slicing level and provides a loss-of-
signal level alarm output. The CDR includes a bit error
rate performance monitor which signals a high bit error
rate condition (associated with excessive incoming
jitter) relative to an externally adjustable bit error rate
threshold.
The option of a reference clock minimizes the CDR
acquisition time and provides a stable reference for
maintaining the output clock when locking to reference
is desired.
4.1. Limiting Amplifier
The limiting amplifier accepts the low-level signal output
from a transimpedance amplifier (TIA). The low-level
signal is amplified to a usable level for the clock and
data
recovery
unit.
The
minimum
input
swing
requirement is specified in Table 2. Larger input
amplitudes (up to the maximum input swing specified in
Table 2) are accommodated without degradation of
performance. The limiting amplifier ensures optimal
data slicing by using a digital dc offset cancellation
technique to remove any dc bias introduced by the
internal amplification stage.
4.2. DSPLL
The Si5023 PLL structure (shown in Figure 1 on page 5)
utilizes Silicon Laboratories' DSPLL technology to
maintain superior jitter performance while eliminating
the need for external loop filter components found in
traditional PLL implementations. This is achieved by
using a digital signal processing (DSP) algorithm to
replace the loop filter commonly found in analog PLL
designs. This algorithm processes the phase detector
error term and generates a digital control value to adjust
the frequency of the voltage-controlled oscillator (VCO).
DSPLL enables clock and data recovery with far less
jitter than is generated using traditional methods and it
eliminates performance degradation caused by external
component aging. In addition, because external loop
filter components are not required, sensitive noise entry
points are eliminated, thus making the DSPLL less
susceptible to board-level noise sources and making
SONET/SDH jitter compliance easier to attain in the
application.
4.3. Multi-Rate Operation
The Si5023 supports clock and data recovery for OC-48
and STM-16 data streams. In addition, the PLL was
designed to operate at data rates up to 2.7 Gbps to
support OC-48/STM-16 applications that employ FEC.
Multi-rate operation is achieved by configuring the
device to divide down the output of the VCO to the
desired data rate. The divide factor is configured by the
RATESEL[0:1] pins. The RATESEL[0:1] configuration
and associated data rates are given in Table 7.
4.4. Operation Without an External
Reference
The Si5023 can perform clock and data recovery
without
an
external
reference
clock.
Tying
the
REFCLK+ input to VDD and REFCLK– to GND
configures the device to operate without an external
reference
clock.
Clock
recovery
is
achieved
by
monitoring the timing quality of the incoming data
relative to the VCO frequency. Lock is maintained by
continuously monitoring the incoming data timing quality
and adjusting the VCO accordingly. Details of the lock
detection and the lock-to-reference functions while in
this mode are described in their respective sections
below.
Note: Without an external reference, the acquisition of data is
dependent solely on the data itself and typically
requires more time to acquire lock than when a refer-
ence is applied.
Table 7. Multi-Rate Configuration
RATESEL
[0:1]
SONET/
SDH
Gigabit
Ethernet
OC-48
with
15/14
FEC
CLK
Divider
11
2.488 Gbps
—
2.67 Gbps
1
01
1.244 Gbps
1.25 Gbps
—
2
10
622.08 Mbps
—
4
00
155.52 Mbps
—
16
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