參數(shù)資料
型號: SI3019-F-GM
廠商: Silicon Laboratories Inc
文件頁數(shù): 113/128頁
文件大小: 0K
描述: IC VOICE GLOBAL DAA PROGR 20QFN
標(biāo)準(zhǔn)包裝: 490
系列: *
Si3050 + Si3011/18/19
Rev. 1.5
85
Reset settings = 0010_0000
Register 31. DAA Control 5
Bit
D7D6D5D4D3D2D1D0
Name
FULL
FOH[1:0]
0
OHS2
0
FILT
LVFD
Type
R/W
RW
R/W
Bit
Name
Function
7
FULL
Full Scale Transmit and Receive Mode. Si3018 and Si3019 line-side only.
0=Default.
1 = Transmit/receive full scale.
This bit changes the full scale of the ADC and DAC from 0 dBm min to +3.2 dBm into a 600
load (or 1 dBV into all reference impedances). When this bit is set, the DCV[1:0] bits
(Register 26) should be set to all 1s. The MINI[1:0] bits also should be set to all 0s. This ensures
correct operation of the full scale mode.
For Si3011 line-side device, always write this bit to zero.
6:5
FOH[1:0] Fast Off-Hook Selection.
These bits determine the length of the off-hook counter. The default setting is 128 ms.
00 = 512 ms
01 = 128 ms
10 = 64 ms
11 = 8 ms
4
Reserved
Always write these bits to zero.
3
OHS2
On-Hook Speed 2.
This bit, in combination with the OHS bit (Register 16) and the SQ[1:0] bits on-hook speeds
specified are measured from the time the OH bit is cleared until loop current equals zero.
OHS
OHS2
SQ[1:0]
Mean On-Hook Speed
0
00
Less than 0.5 ms
0
1
00
3 ms ±10% (meets ETSI standard)
1
X
11
26 ms ±10% (meets Australia spark quenching spec)
2
Reserved
Always write these bits to zero.
1FILT
Filter Pole Selection.
0 = The receive path has a low –3 dBFS corner at 5 Hz.
1 = The receive path has a low –3 dBFS corner at 200 Hz.
0LVFD
Line Voltage Force Disable (Si3011 and Si3019 line-side only).
0 = Normal operation.
1 = The circuitry that forces the LVS register (Register 29) to all 0s at 3 V or less is disabled. The
LVS register may display unpredictable values at voltages between 0 to 2 V. All 0s are displayed
if the line voltage is 0 V.
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