參數(shù)資料
型號(hào)： SAE81C91
廠商： INFINEON TECHNOLOGIES AG
英文描述： Standalone Full-CAN Controller
中文描述： 獨(dú)立全CAN控制器
文件頁(yè)數(shù)： 31/41頁(yè)
文件大?。?/td> 521K
代理商： SAE81C91
07Feb95@09:05h Intermediate Version
Semiconductor Group
30
SAE 81C90/91
Port Control Registers
These registers control the parallel ports P0 and P1 which are provided in the SAE 81C90.
The Port Direction Registers PxPDR
select each port pin separately for input (PxPDR.n=’0’) or
output (PxPDR.n=’1’). After reset the ports are switched as inputs.
The Port Latch Registers PxLR
store the output data for those port pins that are switched to
output.
The Port Pin Registers PxPR
provide the current level of the port pins. These registers can only
be read.
In parallel to the standard CMOS structure there are additional internal pullup devices of about
10...200 k
at each port pin.
Note:
Registers PxPDR and PxPL may be used for general purpose storage if the ports are not
used.
P1PDR
7
6
5
4
3
2
1
0
Address: 2C
H
Reset Value: 00
H
P1PD.7 P1PD.6 P1PD.5 P1PD.4 P1PD.3 P1PD.2 P1PD.1 P1PD.0
rw
rw
rw
rw
rw
rw
rw
rw
P0PDR
7
6
5
4
3
2
1
0
Address: 28
H
Reset Value: 00
H
P0PD.7 P0PD.6 P0PD.5 P0PD.4 P0PD.3 P0PD.2 P0PD.1 P0PD.0
rw
rw
rw
rw
rw
rw
rw
rw
P1LR
7
6
5
4
3
2
1
0
Address: 2E
H
Reset Value: 00
H
P1L.7
P1L.6
P1L.5
P1L.4
P1L.3
P1L.2
P1L.1
P1L.0
rw
rw
rw
rw
rw
rw
rw
rw
P0LR
7
6
5
4
3
2
1
0
Address: 2A
H
Reset Value: 00
H
P0L.7
P0L.6
P0L.5
P0L.4
P0L.3
P0L.2
P0L.1
P0L.0
rw
rw
rw
rw
rw
rw
rw
rw
P1PR
7
6
5
4
3
2
1
0
Address: 2D
H
Reset Value: 00
H
P1P.7
P1P.6
P1P.5
P1P.4
P1P.3
P1P.2
P1P.1
P1P.0
r
r
r
r
r
r
r
r
P0PR
Address: 29
H
Reset Value: 00
H
7
6
5
4
3
2
1
0
P0P.7
P0P.6
P0P.5
P0P.4
P0P.3
P0P.2
P0P.1
P0P.0
r
r
r
r
r
r
r
r
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