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參數資料
| 型號： | SAE81C91 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | Standalone Full-CAN Controller |
| 中文描述： | 獨立全CAN控制器 |
| 文件頁數： | 21/41頁 |
| 文件大?。?/td> | 521K |
| 代理商： | SAE81C91 |
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07Feb95@09:05h Intermediate Version
Semiconductor Group
20
SAE 81C90/91
Notes on Bit TC
Scanning this bit is particularly useful if only one transmission is active. If there are several
transmission jobs at the same time, it is better to scan the transmit-request register, because bit TC
may possibly only be set very briefly between acknowledgment of the previous message and the
start of the next one.
Notes on Bit RES and IM and reset modes
There are three different reset modes implemented in the SAE 81C90/91:
hardware reset (activated by low level on pin RES)
hard software reset (activated by setting both bits RES and IM to 1)
soft software reset (activated by setting bit RES to 1 and bit IM to 0)
The only difference between hardware and hard software reset affect bits RES and IM, that are not
changed by software reset.
With soft software reset the registers RRR1, RRR2, TRSR1, TRSR2, RRPR1 and RRPR2 are
cleared, all bus activities are stopped, the error counters are not cleared, the Bus Off state is
cancelled only after 128 idle phases (according to the CAN protocol 1 idle phase = 11 recessive bits
in sequence). Simply spoken a soft software reset interrupts and cancels all bus activities and - if
necessary - recovers from Bus Off state.
Notes on Bit RS
Bit RS directly reflects the internal status.
RS is ’0’ during transmission or when the SAE 81C90/91 is idle.
RS is ’1’ during reception or during the synchronization after a reset.
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