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參數(shù)資料
| 型號(hào)： | SAE81C91 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | Standalone Full-CAN Controller |
| 中文描述： | 獨(dú)立全CAN控制器 |
| 文件頁數(shù)： | 30/41頁 |
| 文件大小： | 521K |
| 代理商： | SAE81C91 |
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07Feb95@09:05h Intermediate Version
Semiconductor Group
29
SAE 81C90/91
Time Stamp Register Table
Transmit Check Error Counter
Note:
Not defined bit positions must be ’0’ for write accesses.
Transmit Check Data Register
This register supports an error analysis when a transmit check error is encountered. Reading TCD
provides the byte which was actually being sent when the error occurred.
Address
Function
High Byte
30
H
31
H
32
H
33
H
:
Time-Stamp 0
Low Byte
High Byte
Time-Stamp 1
Low Byte
:
:
3C
H
3D
H
3E
H
3F
High Byte
Time-Stamp 6
Low Byte
High Byte
Time-Stamp 7
Low Byte
TCEC
7
6
5
4
3
2
1
0
Address: 15
H
Reset Value: 00
H
-
-
-
-
-
TCECV
-
-
-
-
-
rw
rw
rw
Bit(field)
Function
TCECV
Transmit Check Error Counter Value
Number of errors detected by the transmit check unit.
When a count of 4 is reached an interrupt is generated if enabled.
If bit TCE (CTRL.1) is set to ’1’ the Bus Off status is entered in this case.
TCD
Address: 16
H
Reset Value: XX
H
7
6
5
4
3
2
1
0
Data Byte
r
r
r
r
r
r
r
r
Bit(field)
Function
The data byte which was attempted to be sent while a transmit check error was
encountered.
Data Byte
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