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參數(shù)資料
| 型號(hào)： | SAB88C166W-5M |
| 廠(chǎng)商： | SIEMENS A G |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 16-Bit CMOS Single-Chip Microcontrollers with/without oscillator prescaler with 32 KByte Flash EPROM |
| 中文描述： | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100 |
| 文件頁(yè)數(shù)： | 37/58頁(yè) |
| 文件大小： | 611K |
| 代理商： | SAB88C166W-5M |
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SAB 88C166(W)
Semiconductor Group
36
AC Characteristics
(cont’d)
Multiplexed Bus for the SAB 88C166
V
CC
= 5 V
±
10 %;
T
A
= 0 to + 70 C
C
L
(for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF
ALE cycle time = 6 TCL + 2
t
A
+
t
C
+
t
F
(150 ns at 20-MHz CPU clock without waitstates)
V
SS
= 0 V
for SAB 88C166-5M
Parameter
Symbol
Max. CPU Clock
= 20 MHz
Variable CPU Clock
1/2TCL = 1 to 20 MHz
Unit
min.
15 +
t
A
10 +
t
A
15 +
t
A
15 +
t
A
max.
min.
TCL – 10 +
t
A
–
TCL – 15 +
t
A
–
TCL – 10 +
t
A
–
TCL – 10 +
t
A
–
max.
ALE high time
t
5
CC
t
6
CC
t
7
CC
t
8
CC
–
ns
Address setup to ALE
–
ns
Address hold after ALE
–
ns
ALE falling edge to RD,
WR (with RW-delay)
–
ns
ALE falling edge to RD,
WR (no RW-delay)
t
9
CC
– 10 +
t
A
–
– 10 +
t
A
–
ns
Address float after RD,
WR (with RW-delay)
t
10
CC
–
5
–
5
ns
Address float after RD,
WR (no RW-delay)
t
11
CC
–
30
–
TCL + 5
ns
RD, WR low time
(with RW-delay)
t
12
CC
40 +
t
C
–
2TCL – 10
+
t
C
3TCL – 10
+
t
C
–
–
ns
RD WR low time
(no RW-delay)
t
13
CC
65 +
t
C
–
–
ns
RD to valid data in
(with RW-delay)
t
14
SR
–
30 +
t
C
2TCL – 20
+
t
C
3TCL – 20
+
t
C
3TCL – 20
+
t
A
+
t
C
4TCL – 25
+
2
t
A
+
t
C
–
ns
RD to valid data in
(no RW-delay)
t
15
SR
–
55 +
t
C
–
ns
ALE low to valid data in
t
16
SR
–
55
+
t
A
+
t
C
75
+
2
t
A
+
t
C
–
–
ns
Address to valid data in
t
17
SR
–
–
ns
Data hold after RD
rising edge
t
18
SR
0
0
ns
Data float after RD
t
19
SR
–
35 +
t
F
–
2TCL – 15
+
t
F
–
ns
Data valid to WR
t
22
CC
35 +
t
C
–
2TCL – 15
+
t
C
2TCL – 15
+
t
F
ns
Data hold after WR
t
23
CC
35 +
t
F
–
–
ns
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