參數(shù)資料
型號(hào)： SAA7388GP
廠(chǎng)商： NXP SEMICONDUCTORS
元件分類(lèi)： 微控制器/微處理器
英文描述： Error correction and host interface IC for CD-ROM ELM
中文描述： 8-BIT, 50.4 MHz, MICROCONTROLLER, PQFP80
文件頁(yè)數(shù)： 8/60頁(yè)
文件大?。?/td> 226K
代理商： SAA7388GP
1996 Apr 26
8
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for
CD-ROM (ELM)
SAA7388
6.1
Pin functions
6.1.1
RA0
TO
RA14
External memory address signals.
6.1.2
RA16/CAS
External memory RA16 signal if SRAM or, CAS signal if
DRAM.
6.1.3
RA15/RAS
External memory RA15 signal if SRAM or, RAS signal if
DRAM.
6.1.4
RWE
Write output enable signal for external buffer memory. This
is LOW when the SAA7388 wants to write data into the
external memory.
6.1.5
RD0
TO
RD7
External buffer memory bidirectional data signals.
6.1.6
SFSY
Frame sync for the Q-to-W subcode, indicates when
P-channel is available by a HIGH-to-LOW transition.
Frame 0 is also indicated by no transition on this line.
6.1.7
RCK
In response to SFSY going LOW data is clocked into the
SAA7388 before each rising edge using this clock output.
6.1.8
SUB
Q-to-W subcode is input in response toRCK in 3-wire EIAJ
mode or WS in “V4” mode compatible with the SAA7345.
6.1.9
BCK
Bit clock for the serial data input from the CD decoder.
6.1.10
WS
Word clock for the serial data input from the CD decoder.
6.1.11
DATA
Serial data input from the CD decoder. This may be either
I
2
S-bus or EIAJ 16-bit format.
6.1.12
C2PO
Error flag from the CD decoder. A HIGH indicates that a
byte has not been corrected by the C2 error corrector and
therefore is not valid. This is taken into account by the
SAA7388 error corrector.
6.1.13
SDA
Sub-CPU bidirectional data signal. This signal forms part
of the 3-wire serial interface between the SAA7388 and the
sub-CPU.
6.1.14
SCL
Sub-CPU sync signal. This signal forms part of the 3-wire
serial interface between the SAA7388 and the sub-CPU.
This signal is used to synchronize data transfers between
the sub-CPU and the SAA7388.
6.1.15
INT
Sub-CPU interrupt signal. This active LOW output signals
to the sub-CPU that the SAA7388 has an interrupt request.
6.1.16
RESET
Forcing this input LOW resets the SAA7388.
6.1.17
SYN
Sub-CPU clock signal. This signal forms part of the 3-wire
serial interface between the SAA7388 and the sub-CPU.
This signal is the sub-CPU driven bit clock used to
synchronize the signals on the SDA line.
6.1.18
CS1/HEN
In the ATAPI mode this is the host chip select 1 address
signal. In the Sanyo and Oak compatibility modes setting
this input LOW enables the host interface.
6.1.19
HWR
This active LOW signal is the host write request.
6.1.20
HRD
This active LOW signal is the host read request.
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