參數(shù)資料
型號: SAA7388GP
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Error correction and host interface IC for CD-ROM ELM
中文描述: 8-BIT, 50.4 MHz, MICROCONTROLLER, PQFP80
文件頁數(shù): 26/60頁
文件大?。?/td> 226K
代理商: SAA7388GP
1996 Apr 26
26
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for
CD-ROM (ELM)
SAA7388
7.9
Host registers
7.9.1
S
ANYO COMPATIBILITY MODE
Table 25
Sanyo compatibility mode
Note
1.
Where X = don’t care.
HEN
CMD
HRD
HWR
OPERATION
0
0
0
0
1
0
0
1
1
X
1
0
1
0
X
0
1
0
1
X
write COMIN
read SBOUT
write data
read data
none (note 1)
Fig.3 Sub-CPU interface R/W timing diagram.
handbook, full pagewidth
MGE191
0
SDA
(from sub-CPU)
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCL
SYN
READ/WRITE = 0
READ/WRITE = 1
0
SDA
(from sub-CPU)
1
2
3
4
5
6
7
SDA
(from ELM)
0
1
2
3
4
5
6
7
SCL
SYN
7.9.1.1
COMIN
This is a 12-byte FIFO used for sending commands from
the host to the sub-CPU. When the host writes to the
COMIN register a sub-CPU CMDI interrupt is generated to
indicate there are bytes in the COMIN FIFO. This is
cleared when the sub-CPU empties the FIFO. If the host
writes to the register when the FIFO is full then the
command is ignored.
If the host writes to this register when the CMDBK bit in the
IFCTRL register is asserted then this will terminate any
data or status byte transfers that are in progress.
7.9.1.2
SBOUT
This is a 12 byte FIFO used to transfer status bytes from
the sub-CPU to the host. The host should only access this
register when the STEN pin is LOW indicating that there
are status bytes available.
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