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參數(shù)資料
| 型號： | SAA7381 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | ATAPI CD-R block decoder |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP144 |
| 文件頁數(shù)： | 81/108頁 |
| 文件大?。?/td> | 380K |
| 代理商： | SAA7381 |
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1997 Aug 12
81
Philips Semiconductors
Objective specification
ATAPI CD-R block decoder
SAA7381
Notes
1.
T
cy
is the minimum total cycle time, t
W(DIOR/DIOW)
is the minimum command active time, and t
Wneg(DIOR)
or t
Wneg(DIOW)
,
as appropriate) is the minimum command recovery time or command inactive time. The actual cycle time equals the
sum of the actual command active time and the actual command inactive time. The three timing requirements of T
cy
,
t
W(DIOR/DIOW)
and t
Wneg(DIOR)
or t
Wneg(DIOW)
shall be met. The minimum total cycle time requirement, T
cy
, is greater
than the sum of t
W(DIOR/DIOW)
and t
Wneg(DIOR)
or t
Wneg(DIOW)
. This means a host implementation can lengthen either
or both t
W(DIOR/DIOW)
or t
Wneg(DIOR)
or t
Wneg(DIOW)
to ensure that T
cy
is equal to the value reported in the devices
identify drive data. A device implementation shall support any legal host implementation.
The original ATA standard defined a maximum value for t
h(DIOR)
. The meaning of this value was not clear. This
parameter has been renamed to t
d(DMACK-z)
and specifies the time from the negation edge of DMACK to the time the
device data signals are no longer driven by the device (3-state). The t
d(DMACK-z)
parameter applies only at the end of
a multi-word DMA cycle, i.e., when DMACK is negated. The device may actively drive the Device Data signals, or
may 3-state the device data signals, while DMACK is active from the first time that DIOR is asserted until DMACK is
negated as long as t
ACC(DIOR)
and t
h(DIOR)
requirements are met.
2.
t
d(DIOW-DMARQ)
delay time from DIOW to DMARQ
Mode 0
Mode 1
Mode 2
note 2
Mode 0
Mode 1
Mode 2
40
40
35
ns
ns
ns
t
d(DMACK-z)
delay time from DMACK to 3-state
20
25
25
ns
ns
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
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