參數(shù)資料
型號: SAA7381
廠商: NXP SEMICONDUCTORS
元件分類: 消費家電
英文描述: ATAPI CD-R block decoder
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP144
文件頁數(shù): 24/108頁
文件大?。?/td> 380K
代理商: SAA7381
1997 Aug 12
24
Philips Semiconductors
Objective specification
ATAPI CD-R block decoder
SAA7381
Table 29
Auxiliary segment pointer
ADDRESS
NAME
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FF29H
FF28H
AUXSEGMENT-L
AUXSEGMENT-H
s7
s6
s5
s4
s12
s3
s11
s2
s10
s1
s9
s0
s8
The auxiliary segment pointer points at a group of
segments which hold the data FIFOs used in the
SAA7381. These are the ‘large’ FIFOs rather than the
small resynchronizing FIFOs inside the SAA7381.
The subcode input/output and n = 1 I
2
S-bus interfaces use
these FIFOs (in addition, the shadow debug registers can
use some of this space).
The FIFOs are arranged to optimally occupy a contiguous
group of segments in the external RAM.
7.3
Multimedia output interface
This block deals with subcode input and output in addition
to an audio output which is independent of the I
2
S-bus
input output path connected to the CD-R engine.
Q and R-W subcode features:
Supports semiautomatic de-interleaving/interleaving
Subcode sync is aligned with the start of the current
block in RAM
Supports subcode resynchronization when subcode
sync is lost
Supports Philips ‘V4’ and 3-wire formats
Has selectable polarity on RCK
Uses WSI1 pin as timing reference
Supports regeneration of subcode from IEC 958 output
using WS2 as timing reference
Can accept subcode input while I
2
S-bus from CD-DSP
is oversampled audio at n = 2 or n = 4 oversample
Audio output (multimedia) features:
Has data output for simple audio or digital video for
n = 1 or n = 2 rate regardless of input CD-DSP data rate
4096-byte FIFO for audio samples, requires firmware
polling for refills using the block copy engine
Permits CAV and quasi-CLV systems to maintain n = 1
audio output
Basic channel swap, mono-L or mono-R modes,
includes muting and L + R summed mono
IEC 958 output with subcode Q-W for use in CAV and
other modes where there is no n = 1 clock in the
CD-DSP subsystem
– IEC 958 interface has fully programmable category
code and copyright bits for flexibility
– Subcode on IEC 958 is only available in CD-ROM
mode, because the subcode output FIFO is shared.
Master and slave I
2
S-bus modes are available
– IEC 958 is only available when the I
2
S-bus is in the
master mode.
Can be configured to provide a clock for an external
CD-DSP function via the MCK pin
Can operate in 64f
s
or 48f
s
I
2
S-bus modes
IEC 958 can operate at n = 2 although not permitted by
standard.
7.3.1
S
UBCODE INPUT BLOCK
7.3.1.1
Q-W subcode handling
The subcode data is initially converted from
serial-to-parallel format and is then handled as Q-W bytes.
The de-interleaving is performed by a de-interleaving
block copy mode in the memory processor’s block copy
engine. Subcode blocks will always be aligned with a block
of CD-ROM data, although the subcode Minutes,
Seconds, Frames (MSF) absolute time may have an
uncertainty of
±
5 frames in terms of the actual CD-ROM
block it is referring to. This offset is unknown but consistent
in any given application. The block copy engine will be
automatically triggered when the subcode synchronization
is found.
The error corrector will then compute the CRC syndrome
of the subcode and deposit it in the CRC bytes.
The sub-CPU will have to perform the actual correction if a
non-zero syndrome appears.
This syndrome, if calculated during encoding by the
ERCO, can be used as the CRC written to disc for the
subcode.
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