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參數(shù)資料
| 型號(hào)： | SAA7325 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)(具有綜合數(shù)模轉(zhuǎn)換器（DAC）的數(shù)字伺服處理器和光盤譯碼器) |
| 中文描述： | 數(shù)字伺服處理器和光盤解碼器集成了援會(huì)（CD10型二）（具有綜合數(shù)模轉(zhuǎn)換器（DAC）的的數(shù)字伺服處理器和光盤譯碼器） |
| 文件頁(yè)數(shù)： | 53/68頁(yè) |
| 文件大?。?/td> | 281K |
| 代理商： | SAA7325 |
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2000 Jun 26
53
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)
SAA7325
10 OPERATING CHARACTERISTICS (SUBCODE INTERFACE TIMING)
V
DD
= 3.0 to 3.6 V; V
SS
= 0 V; T
amb
=
10 to +70
°
C; unless otherwise specified.
Note
1.
In lock-to-disc mode, the subcode timing is directly related to the disc speed factor ‘d’. In normal, single speed
operation, d = 1.
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Subcode interface timing; d = 1 for normal operation;
see Fig.32; note 1
I
NPUT
:
PIN
RCK
t
CLKH
t
CLKL
t
r
t
f
t
d(SFSY-RCK)
O
UTPUTS
:
PINS
SBSY, SFSY
AND
SUB (C
L
= 20
P
F)
T
cy(block)
block cycle time
t
W(SBSY)
SBSY pulse width
T
cy(frame)
frame cycle time
t
W(SFSY)
SFSY pulse width (3-wire mode only)
t
SFSYH
SFSY HIGH time
t
SFSYL
SFSY LOW time
t
d(SFSY-SUB)
delay time SFSY to SUB (P data) valid
t
d(RCK-SUB)
delay time RCK falling to SUB
t
h(RCK-SUB)
hold time RCK to SUB
input clock HIGH time
input clock LOW time
input clock rise time
input clock fall time
delay time SFSY to RCK
2/d
2/d
10/d
4/d
4/d
6/d
6/d
80/d
80/d
20/d
μ
s
μ
s
ns
ns
μ
s
12.0/d
122/d
13.3/d
136/d
14.7/d
300/d
150/d
366/d
66/d
84/d
1/d
0
0.7/d
ms
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
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