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參數(shù)資料
| 型號： | SAA7325 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)(具有綜合數(shù)模轉(zhuǎn)換器（DAC）的數(shù)字伺服處理器和光盤譯碼器) |
| 中文描述： | 數(shù)字伺服處理器和光盤解碼器集成了援會（CD10型二）（具有綜合數(shù)模轉(zhuǎn)換器（DAC）的的數(shù)字伺服處理器和光盤譯碼器） |
| 文件頁數(shù)： | 41/68頁 |
| 文件大小： | 281K |
| 代理商： | SAA7325 |
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2000 Jun 26
41
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)
SAA7325
6
(motor output
configuration)
0110
XX00
XX01
XX10
XX11
00XX
01XX
10XX
11XX
XX00
XX10
motor power maximum 37%
motor power maximum 50%
motor power maximum 75%
motor power maximum 100%
MOTO1, MOTO2 pins 3-state
motor PWM mode
motor PDM mode
motor CDV mode
interrupt signal from servo at STATUS pin
status bit from decoder status register at STATUS
pin
DAC data normal value
DAC data inverted value
left channel first at DAC (WCLK normal)
right channel first at DAC (WCLK inverted)
see Table 15
reset
reset
reset
7
(DAC output
and status
control)
0111
X0XX
X1XX
0XXX
1XXX
reset
reset
8
(PLL loop filter
bandwidth)
9
(PLL
equalization)
1001
0011
0001
0010
0100
0101
XX0X
XX1X
X0X0
X0X1
X1X0
X1X1
0XXX
1XXX
00XX
PLL loop filter equalization
PLL 30 ns over-equalization
PLL 15 ns over-equalization
PLL 15 ns under-equalization
PLL 30 ns under-equalization
EBU data before concealment
EBU data after concealment and fade
level II clock accuracy (<1000 ppm)
level I clock accuracy (<50 ppm)
level III clock accuracy (>1000 ppm)
EBU off - output low
flags in EBU off
flags in EBU on
33.8688 MHz crystal present, or 8.4672 MHz (or
16.9344 MHz) crystal with SELPLL set HIGH
16.9344 MHz crystal present
standby 1: ‘CD-STOP’ mode
standby 2: ‘CD-PAUSE’ mode
operating mode
reset
reset
reset
reset
reset
A
(EBU output)
1010
B
(operating
frequency)
1011
01XX
0X00
0X10
0X11
reset
REGISTER
ADDRESS
DATA
FUNCTION
INITIAL
(1)
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