參數(shù)資料
型號(hào)： SAA7325
廠商： NXP Semiconductors N.V.
英文描述： Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)(具有綜合數(shù)模轉(zhuǎn)換器（DAC）的數(shù)字伺服處理器和光盤(pán)譯碼器)
中文描述： 數(shù)字伺服處理器和光盤(pán)解碼器集成了援會(huì)（CD10型二）（具有綜合數(shù)模轉(zhuǎn)換器（DAC）的的數(shù)字伺服處理器和光盤(pán)譯碼器）
文件頁(yè)數(shù)： 14/68頁(yè)
文件大?。?/td> 281K
代理商： SAA7325
2000 Jun 26
14
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)
SAA7325
Fig.9 Subcode format and timing on pin V4.
W96
1
Q
R
S
T
U
V
W
1
Q
200
μ
s
min
11.3
μ
s
11.3
μ
s min
90
μ
s max
MGL719
7.6
FIFO and error corrector
The SAA7325 has a
±
8 frame FIFO. The error corrector is
a t = 2, e = 4 type, with error corrections on both C1
(32 symbol)and C2(28 symbol)frames.Foursymbolsare
used from each frame as parity symbols. This error
corrector can correct up to two errors on the C1 level and
up to four errors on the C2 level.
The error corrector also contains a flag processor. Flags
are assigned to symbols when the error corrector cannot
ascertain if the symbols are definitely good. C1 generates
output flags which are read after (de-interleaving) by C2,
to help in the generation of C2 output flags.
The C2 output flags are used by the interpolator for
concealment of uncorrectable errors. They are also output
via the EBU signal (DOBM). The EF output will flag bytes
in error in both audio and CD-ROM modes.
7.6.1
F
LAGS OUTPUT
(CFLG)
The flags output pin CFLG shows the status of the error
corrector and interpolator and is updated every frame
(7.35
×
n kHz). In the SAA7325 chip a 1-bit flag is present
on the CFLG pin as illustrated in Fig.10. This signal shows
the status of the error corrector and interpolator.
The first flag bit, F1, is the absolute time sync signal, the
FIFO-passed subcode sync and relates the position of the
subcode sync to the audio data (DAC output). This flag
mayalsobeusedinasuperFIFOorinthesynchronization
of different players. The output flags can be made
available at bit 4 of the EBU data format (LSB of the 24-bit
data word), if selected by decoder register A.
Fig.10 Flag output timing diagram.
handbook, full pagewidth
F1
F2
F3
F4
F5
F6
F7
F8
F1
F8
11.3
μ
s
33.9
μ
s
33.9
μ
s
MGL720
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