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參數(shù)資料
| 型號(hào)： | SAA7325 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)(具有綜合數(shù)模轉(zhuǎn)換器（DAC）的數(shù)字伺服處理器和光盤(pán)譯碼器) |
| 中文描述： | 數(shù)字伺服處理器和光盤(pán)解碼器集成了援會(huì)（CD10型二）（具有綜合數(shù)模轉(zhuǎn)換器（DAC）的的數(shù)字伺服處理器和光盤(pán)譯碼器） |
| 文件頁(yè)數(shù)： | 42/68頁(yè) |
| 文件大?。?/td> | 281K |
| 代理商： | SAA7325 |
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2000 Jun 26
42
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)
SAA7325
Note
1.
The initial column shows the power-on reset state.
C
(versatile pins
interface)
1100
XXX1
XXX0
external off-track signal input at V1
internal off-track signal used (V1 may be read via
status)
kill-L at KILL output, kill-R at V3 output
V3 = 0; single KILL output
V3 = 1; single KILL output
4-line motor (using V4 and V5)
Q-to-W subcode at V4
V4 = 0
V4 = 1
de-emphasis signal at V5, no internal
de-emphasis filter
V5 = 0
V5 = 1
audio features disabled
audio features enabled
lock-to-disc mode disabled
lock-to-disc mode enabled
motor brakes to 12%
motor brakes to 6%
subcode interface off
subcode interface on
4-wire subcode
3-wire subcode
SHADEN = 0; shadow registers not enabled;
addresses will be decoded by main decoder
registers
SHADEN = 1; shadow registers enabled; all
subsequent addresses will be decoded by
shadow registers, not decoder registers
reset
XX0X
001X
011X
0000
XX01
XX10
XX11
01XX
reset
reset
D
(versatile pins
interface)
1101
10XX
11XX
00XX
01XX
XX0X
XX1X
XXX0
XXX1
X0XX
X1XX
0XXX
1XXX
XXX0
reset
reset
reset
reset
reset
reset
reset
E
1110
F
(subcode
interface and
shadow
register
enable)
1111
XXX1
REGISTER
ADDRESS
DATA
FUNCTION
INITIAL
(1)
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