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參數(shù)資料
| 型號(hào)： | SAA5500PS/NNNN |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 12 MHz, MICROCONTROLLER, PDIP52 |
| 封裝： | 0.600 INCH, PLASTIC, SDIP-52 |
| 文件頁(yè)數(shù)： | 68/80頁(yè) |
| 文件大?。?/td> | 340K |
| 代理商： | SAA5500PS/NNNN |
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1999 Oct 27
70
Philips Semiconductors
Preliminary specication
Standard TV microcontrollers with
On-Screen Display (OSD)
SAA55xx
22.1
I2C-bus characteristics
Table 25 I2C-bus characteristics
Notes
1. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIL(min) of the SCL
signal) in order to bridge the undefined region of the falling edge of SCL.
2. The maximum fHD;DAT has only to be met if the device does not stretch the LOW period tLOW of the SCL signal.
3. A fast-mode I2C-bus device can be used in a standard mode I2C-bus system but the requirement tSU;DAT ≥250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal.
If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
tr(max) +tSU;DAT = 1000 + 250 +1250 ns (according to the standard mode I2C-bus specification) before the SCL line
is released.
SYMBOL
PARAMETER
FAST-MODE I2C-bus
UNIT
MIN.
MAX.
fSCL
SCL clock frequency
0
400
kHz
tBUF
bus free time between a STOP and START condition
1.3
s
tHD;STA
hold time (repeated) START condition. After this period, the
rst clock pulse is generated.
0.6
s
tLOW
LOW period of the SCL clock
1.3
s
tHIGH
HIGH period of the SCL clock
0.6
s
tSU;STA
set-up time for a repeated START condition
0.6
s
tHD;DAT
data hold time; notes 1 and 2
0
0.9
s
tSU;DAT
data set-up time, note 3
100
ns
tr
rise time of both SDA and SCL signals
20
300
ns
tf
fall time of both SDA and SCL signals
20
300
ns
tSU;STO
set-up time for STOP condition
0.6
s
Cb
capacitive load for each bus line
400
pF
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