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參數(shù)資料
| 型號： | SAA5500PS/NNNN |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 12 MHz, MICROCONTROLLER, PDIP52 |
| 封裝： | 0.600 INCH, PLASTIC, SDIP-52 |
| 文件頁數(shù)： | 38/80頁 |
| 文件大?。?/td> | 340K |
| 代理商： | SAA5500PS/NNNN |
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1999 Oct 27
43
Philips Semiconductors
Preliminary specication
Standard TV microcontrollers with
On-Screen Display (OSD)
SAA55xx
18.1.1
CVBS SWITCH
The CVBS switch is used to select the required analog
input depending on the value of TXT8.CVBS1/CVBS0.
18.1.2
ANALOG-TO-DIGITAL CONVERTER
The output of the CVBS switch is passed to a
differential-to-single-ended converter, although in this
device it is used in single-ended configuration with a
reference. The analog output of the differential amplifier is
converted into a digital representation by a full flash ADC
with a sampling rate of 12 MHz.
18.1.3
MULTI-RATE VIDEO INPUT PROCESSOR
The multi-rate video input processor is a Digital Signal
Processor designed to extract the data and recover the
clock from a digitised CVBS signal.
18.1.4
DATA STANDARDS
The data and clock standards that can be recovered are
shown in Table 11.
Table 11 Data slicing standards
18.1.5
DATA CAPTURE TIMING
The Data Capture timing section uses the synchronisation
information extracted from the CVBS signal to generate
the required horizontal and vertical reference timings.
The timing section automatically recognises and selects
the appropriate timings for either 625 (50 Hz)
synchronisation or 525 (60 Hz) synchronisation. A flag
TXT12.VIDEO SIGNAL QUALITY is set when the timing
section is locked correctly to the incoming CVBS signal.
When TXT12.VIDEO SIGNAL QUALITY is set another
flag TXT12.525/625 SYNC can be used to identify the
standard.
18.1.6
ACQUISITION
The acquisition sections extracts the relevant information
from the serial stream of data from the MulVIP and stores
it in memory.
18.1.6.1
Making a page request
A page is requested by writing a series of bytes into the
TXT3.PRD<4:0> SFR which corresponds to the number of
the page required. The bytes written into TXT3 are stored
in a RAM with an auto-incrementing address. The start
address for the RAM is set using the TXT2.SC<2:0> to
define which part of the page request is being written, and
TXT2.REQ<3:0> is used to define which of the 10 page
requests is being modified. If TXT2.REQ<3:0> is greater
than 09H, then data being written to TXT3 is ignored.
Table 12 shows the contents of the page request RAM.
Up to 10 pages of teletext can be acquired on the 10 page
device, when TXT1.EXT PKT OFF is set to logic 1, and up
to 9 pages can be acquired when this bit is set to logic 0.
For a 20 page device the 10 page acquisition channels are
banked, the bank being selected using TXT2.ACQ BANK.
If the ‘DO CARE’ bit for part of the page number is set to
logic 0 then that part of the page number is ignored when
the teletext decoder is deciding whether a page being
received off air should be stored or not. For example, if the
‘DO CARE’ bits for the four subcode digits are all set to
logic 0 then every subcode version of the page will be
captured.
Table 12 The contents of the Page request RAM
DATA STANDARD
CLOCK RATE
(MHz)
625 WST
6.9375
525 WST
5.7272
VPS
5.0
WSS
5.0
START
COLUMN
PRD4
PRD3
PRD2
PRD1
PRD0
0
DO CARE
Magazine
HOLD MAG2 MAG1 MAG0
1
DO CARE
Page Tens
PT3
PT2
PT1
PT0
2
DO CARE
Page Units
PU3
PU2
PU1
PU0
3
DO CARE
Hour Tens
X
HT1
HT0
4
DO CARE
Hours
Units
HU3
HU2
HU1
HU0
5
DO CARE
Minutes
Tens
X
MT2
MT1
MT0
6
DO CARE
Minutes
Units
MU3
MU2
MU1
MU0
7
X
XXE1
E0
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