![](http://datasheet.mmic.net.cn/390000/S75PL127J_datasheet_16832152/S75PL127J_52.png)
August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
S29PL127J/S29PL064J/S29PL032J for MCP
53
P r e l i m i n a r y
During the Embedded Program algorithm, the device outputs on DQ7 the complement
of the datum programmed to DQ7. This DQ7 status also applies to programming during
Erase Suspend. When the Embedded Program algorithm is complete, the device out-
puts the datum programmed to DQ7. The system must provide the program address
to read valid status information on DQ7. If a program address falls within a protected
sector, Data# Polling on DQ7 is active for approximately 1 μs, then that bank returns
to the read mode.
During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7.
When the Embedded Erase algorithm is complete, or if the bank enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide
an address within any of the sectors selected for erasure to read valid status in-
formation on DQ7.
After an erase command sequence is written, if all sectors selected for erasing
are protected, Data# Polling on DQ7 is active for approximately 400 μs, then the
bank returns to the read mode. If not all selected sectors are protected, the Em-
bedded Erase algorithm erases the unprotected sectors, and ignores the selected
sectors that are protected. However, if the system reads DQ7 at an address within
a protected sector, the status may not be valid.
When the system detects DQ7 has changed from the complement to true data,
it can read valid data at DQ15–DQ0 on the
following
read cycles. Just prior to the
completion of an Embedded Program or Erase operation, DQ7 may change asyn-
chronously with DQ15–DQ0 while Output Enable (OE#) is asserted low. That is,
the device may change from providing status information to valid data on DQ7.
Depending on when the system samples the DQ7 output, it may read the status
or valid data. Even if the device has completed the program or erase operation
and DQ7 has valid data, the data outputs on DQ15–DQ0 may be still invalid. Valid
data on DQ15–DQ0 will appear on successive read cycles.
Table 15
shows the outputs for Data# Polling on DQ7. 6 shows the Data# Polling
algorithm. 18 in the AC Characteristic section shows the Data# Polling timing
diagram.