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參數(shù)資料
| 型號： | S75PL127J |
| 廠商： | Spansion Inc. |
| 英文描述： | Power supply woltage of 2.7 to 3.1 volt |
| 中文描述： | 功率2月7號至三月一日伏的電源woltage |
| 文件頁數(shù)： | 45/183頁 |
| 文件大?。?/td> | 1409K |
| 代理商： | S75PL127J |
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46
S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
P r e l i m i n a r y
operation. The program command sequence should be reinitiated once that bank
has returned to the read mode, to ensure data integrity. Note that the SecSi Sec-
tor, autoselect and CFI functions are unavailable when the SecSi Sector is
enabled.
Programming is allowed in any sequence and across sector boundaries.
A bit
cannot be programmed from “0” back to a “1.”
Attempting to do so may
cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate
the operation was successful. However, a succeeding read will show that the data
is still “0.” Only erase operations can convert a “0” to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program data to a bank faster
than using the standard program command sequence. The unlock bypass com-
mand sequence is initiated by first writing two unlock cycles. This is followed by
a third write cycle containing the unlock bypass command, 20h. That bank then
enters the unlock bypass mode. A two-cycle unlock bypass program command
sequence is all that is required to program in this mode. The first cycle in this se-
quence contains the unlock bypass program command, A0h; the second cycle
contains the program address and data. Additional data is programmed in the
same manner. This mode dispenses with the initial two unlock cycles required in
the standard program command sequence, resulting in faster total programming
time.
Table 13
shows the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock By-
pass Reset commands are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset command sequence. (See Table 14)
The device offers accelerated program operations through the WP#/ACC pin.
When the system asserts V
HH
on the WP#/ACC pin, the device automatically en-
ters the Unlock Bypass mode. The system may then write the two-cycle Unlock
Bypass program command sequence. The device uses the higher voltage on the
WP#/ACC pin to accelerate the operation.
Note that the WP#/ACC pin must not
be at V
HH
any operation other than accelerated programming, or device damage
may result. In addition, the WP#/ACC pin must not be left floating or uncon-
nected; inconsistent behavior of the device may result.
4 illustrates the algorithm for the program operation. Refer to the Erase/Program
Operations table in the AC Characteristics section for parameters, and
Figure 14
for timing diagrams.
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