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參數(shù)資料
| 型號： | S75PL127J |
| 廠商： | Spansion Inc. |
| 英文描述： | Power supply woltage of 2.7 to 3.1 volt |
| 中文描述： | 功率2月7號至三月一日伏的電源woltage |
| 文件頁數(shù)： | 17/183頁 |
| 文件大小： | 1409K |
| 代理商： | S75PL127J |
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18
S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
P r e l i m i n a r y
Device Bus Operations
This section describes the requirements and use of the device bus operations,
which are initiated through the internal command register. The command register
itself does not occupy any addressable memory location. The register is a latch
used to store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as inputs to
the internal state machine. The state machine outputs dictate the function of the
device.
Table 1
lists the device bus operations, the inputs and control levels they
require, and the resulting output. The following subsections describe each of
these operations in further detail.
Legend:
L= Logic Low = V
IL
, H = Logic High = V
IH
,
V
ID
= 11.5-12.5 V, V
HH
= 8.5-9.5 V, X = Don’t Care,
Notes:
1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the
High Voltage Sector Protection section.
2. WP#/ACC must be high when writing to upper two and lower two sectors.
SA = Sector Address, A
IN
= Address In, D
IN
= Data
In, D
OUT
= Data Out
Requirements for
Reading Array Data
To read array data from the outputs, the system must drive the OE# and appro-
priate CE# pins. OE# is the output control and gates array data to the output
pins. WE# should remain at V
IH
.
The internal state machine is set for reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the memory
content occurs during the power transition. No command is necessary in this
mode to obtain array data. Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data on the device data
outputs. Each bank remains enabled for read access until the command register
contents are altered.
Refer to
Table 19
for timing specifications and to
Figure 11
for the timing diagram.
I
CC1
in the DC Characteristics table represents the active current specification for
reading array data.
Random Read (Non-Page Read)
Address access time (t
ACC
) is equal to the delay from stable addresses to valid
output data. The chip enable access time (t
CE
) is the delay from the stable ad-
dresses and stable CE# to valid data at the output inputs. The output enable ac-
cess time is the delay from the falling edge of the OE# to valid data at the output
inputs (assuming the addresses have been stable for at least t
ACC
–t
OE
time).
Table 1. PL127J Device Bus Operations
Operation
CE#
OE#
WE#
RESET#
WP#/ACC
Addresses
(Amax–A0)
DQ15–
DQ0
Read
L
L
H
H
X
A
IN
D
OUT
Write
L
H
L
H
X (Note 2)
A
IN
D
IN
Standby
V
IO
±
0.3 V
X
X
V
IO
±
0.3 V
X (Note 2)
X
High-Z
Output Disable
L
H
H
H
X
X
High-Z
Reset
X
X
X
L
X
X
High-Z
Temporary Sector Unprotect (High Voltage)
X
X
X
V
ID
X
A
IN
D
IN
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