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參數(shù)資料
| 型號： | S29PL256N70GFW003 |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory |
| 中文描述： | 16M X 16 FLASH 3V PROM, 70 ns, PBGA84 |
| 封裝： | 8 X 11.60 MM, LEAD FREE, FBGA-84 |
| 文件頁數(shù)： | 49/74頁 |
| 文件大?。?/td> | 1968K |
| 代理商： | S29PL256N70GFW003 |
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June 6, 2007 S29PL-N_00_A5
S29PL-N MirrorBit
Flash Family
49
D a t a
S h e e t
( P r e l i m i n a r y )
8.7
Hardware Data Protection Methods
The device offers data protection at the sector level via hardware control:
When WP#/ACC is at V
IL
, the four outermost sectors are locked (device specific).
There are additional methods by which intended or accidental erasure of any sectors can be prevented via
hardware means. The following subsections describes these methods:
8.7.1
WP# Method
The Write Protect feature provides a hardware method of protecting the four outermost sectors. This function
is provided by the WP#/ACC pin and overrides the previously discussed Sector Protection/Unprotection
method.
If the system asserts V
IL
on the WP#/ACC pin, the device disables program and erase functions in the
outermost
boot sectors. The outermost boot sectors are the sectors containing both the lower and upper set
of sectors in a dual-boot-configured device.
If the system asserts V
IH
on the WP#/ACC pin, the device reverts to whether the boot sectors were last set to
be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether
they were last protected or unprotected.
Note that the WP#/ACC pin must not be left floating or unconnected as inconsistent behavior of the device
may result.
The WP#/ACC pin must be held stable during a command sequence execution
8.7.2
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the device does not accept any write cycles. This protects data during V
CC
power-up and power-down.
The command register and all internal program/erase circuits are disabled, and the device resets to reading
array data. Subsequent writes are ignored until V
CC
is greater than V
LKO
. The system must provide the
proper signals to the control inputs to prevent unintentional writes when V
CC
is greater than V
LKO
.
8.7.3
Write Pulse
Glitch Protection
Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
8.7.4
Power-Up Write Inhibit
If WE# = CE# = RESET# = V
IL
and OE# = V
IH
during power up, the device does not accept commands on the
rising edge of WE#. The internal state machine is automatically reset to the read mode on powerup.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| S29PL256N70GFWW00 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory |
| S29PL256N70GFWW02 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory |
| S29PL256N70GFWW03 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory |
| S29PL256N80FAI000 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory |
| S29PL256N80FAI002 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory |
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