參數(shù)資料
型號(hào)： S25FL004AOLMAI001
廠商： Spansion Inc.
英文描述： 4-Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface
中文描述： 4兆位閃存的CMOS 3.0伏，50赫茲SPI總線接口內(nèi)存
文件頁(yè)數(shù)： 24/39頁(yè)
文件大?。?/td> 945K
代理商： S25FL004AOLMAI001
22
S25FL Family (Serial Peripheral Interface) S25FL004A
S25FL004A_00_A1 March 28, 2005
A d v a n c e I n f o r m a t i o n
When Chip Select (CS#) is driven High, the device is put in the Stand-by Power
mode. Once in the Stand-by Power mode, the device waits to be selected, so that
it can receive, decode and execute instructions.
Table 6. Read Identification (RDID) Data-Out Sequence
Page Program (PP)
The Page Program (PP) instruction allows bytes to be programmed in the memory
(changing bits from
1
to
0
). Before it can be accepted, a Write Enable (WREN)
instruction must previously have been executed. After the Write Enable (WREN)
instruction is decoded, the device sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by driving Chip Select (CS#) Low,
followed by the instruction code, three address bytes and at least one data byte
on Serial Data Input (SI). Chip Select (CS#) must be driven Low for the entire
sequence duration.
The instruction sequence is shown in
Figure 12, on page 23
.
If more than 256 bytes are sent to the device, the addressing wraps to the be-
ginning of the same page, previously latched data are discarded and the last 256
data bytes are guaranteed to be programmed correctly within the same page. If
fewer than 256 Data bytes are sent to device, they are correctly programmed at
the requested addresses without having any effects on the other bytes of the
same page.
Chip Select (CS#) must be driven High after the eighth bit of the last data byte
is latched in, otherwise the Page Program (PP) instruction is not executed. As
soon as Chip Select (CS#) is driven High, the self-timed Page Program cycle
(whose duration is t
PP
) is initiated. While the Page Program cycle is in progress,
the Status Register may be read to check the Write In Progress (WIP) bit value.
The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle,
and is 0 when it is completed. At some unspecified time before the cycle is com-
pleted, the Write Enable Latch (WEL) bit is reset.
A Page Program (PP) instruction applied to a page that is protected by the Block
Protect (BP2, BP1, BP0) bits (see
Table 2, on page 11
) is not executed.
Manufacturer Identification
Device Identification
Memory Type
Memory Capacity
01h
02h
12h
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S25FL004AOLMAI002 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:4-Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface
S25FL004AOLMAI003 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:4-Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface
S25FL004AOLMFI000 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:4-Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface
S25FL004AOLMFI001 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:4-Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface
S25FL004AOLMFI002 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:4-Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface
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