參數(shù)資料
型號(hào)： S25FL004AOLMAI001
廠商： Spansion Inc.
英文描述： 4-Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface
中文描述： 4兆位閃存的CMOS 3.0伏，50赫茲SPI總線接口內(nèi)存
文件頁(yè)數(shù)： 23/39頁(yè)
文件大?。?/td> 945K
代理商： S25FL004AOLMAI001
March 28, 2005 S25FL004A_00_A1
S25FL Family (Serial Peripheral Interface) S25FL004A
21
A d v a n c e I n f o r m a t i o n
The (FAST_READ) instruction is terminated by driving Chip Select (CS#) High.
Chip Select (CS#) can be driven High at any time during data output. Any
(FAST_READ) instruction, while an Erase, Program or Write cycle is in progress,
is rejected without having any effects on the cycle that is in progress.
Figure 10. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence
Read Identification (RDID)
The Read Identification (RDID) instruction allows the 8-bit manufacturer identifi-
cation to be read, followed by two bytes of the device identification.
The manufacturer identification byte is assigned by JEDEC, and has a value of 01h
for Spansion products. The device identification is assigned by the device man-
ufacturer, and indicates the memory type in the first byte (02h), and the device’s
memory capacity in the second byte (12h).
Any Read Identification (RDID) instruction executed while an Erase, Program, or
Write Status Register cycle is in progress is not decoded, and has no effect on the
cycle that is in progress.
The device is first selected by driving Chip Select (CS#) Low. Then, the 8-bit in-
struction code for the instruction is shifted in, with each bit being latched in on
SI during the rising edge of SCK. This is followed by the 24-bit device identifica-
tion, stored in the memory, being shifted out on Serial Data Output (SO), with
each bit being shifted out during the falling edge of Serial Clock (SCK).
The instruction sequence is shown in
Figure 11
.
Figure 11. Read Identification (RDID) Instruction Sequence and Data-Out Sequence
Driving CS# high after the Device Identification is read at least once, terminates
the READ_ID instruction. The Read Identification (RDID) instruction can also be
terminated by driving CS# High at any time during data output.
CS#
SCK
SI
SO
Instruction
24-Bit
Dummy Byte
High Impedance
DATA OUT 1
DATA OUT 2
MSB
MSB
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33
34 35 36 37 38 39
40 41
42 43 44 45 46
47
23 22 21
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
0
1
2
4
5
6
7
8
9
10 11 12
13 14 15 16
17 18
28 29 30 31
Instruction
MSB
Manufacturer Identification
Device Identification
High Impedance
0
1
2
3
13
14
15
CS#
SCK
SI
SO
3
相關(guān)PDF資料
PDF描述
S25FL004AOLMAI002 4-Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface
S25FL004AOLMAI003 4-Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface
S25FL004AOLMFI000 4-Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface
S25FL004AOLMFI001 4-Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S25FL004AOLMAI002 制造商:SPANSION 制造商全稱:SPANSION 功能描述:4-Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface
S25FL004AOLMAI003 制造商:SPANSION 制造商全稱:SPANSION 功能描述:4-Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface
S25FL004AOLMFI000 制造商:SPANSION 制造商全稱:SPANSION 功能描述:4-Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface
S25FL004AOLMFI001 制造商:SPANSION 制造商全稱:SPANSION 功能描述:4-Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface
S25FL004AOLMFI002 制造商:SPANSION 制造商全稱:SPANSION 功能描述:4-Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface
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