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參數(shù)資料
| 型號(hào)： | S1C6S460D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 2 MHz, MICROCONTROLLER, UUC124 |
| 封裝： | 4.69 X 4.68 MM, DIE-124 |
| 文件頁數(shù)： | 98/107頁 |
| 文件大?。?/td> | 788K |
| 代理商： | S1C6S460D |
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82
EPSON
S1C6S460 TECHNICAL MANUAL
CHAPTER 12: SUMMARY OF NOTES
Output port (Rxx)
(1) When BZ, BZ, FOUT, FOUT, and PTCLK (DC) are selected by mask option, a hazard may be observed
in the output waveform when the data of the output register changes.
(2) Because the R00–R03, R10–R13, R20–R23, and R30–R32 (R33) ports gain high impedance during initial
reset, be careful when using them as interface with external devices and the like.
(3) When R33 port is selected for 2 states and DC (PTCLK) output by mask option, R33 terminal becomes
undefined at initial reset.
I/O port (Pxx)
(1) When the I/O port is set at output mode, and low impedance load is connected to the port terminal,
the data written and read may differ.
(2) If the state of the I/O port meets all of the following 4 conditions, the reading data will be undefined:
The input/output mode is set at output mode
Output specification is set at Nch open drain
The content of the data register is "1"
The pull up resistor turned is OFF
(3) When P30–P33 has been set as the output exclusive in the mask option, a pull up resistor cannot be
added even if the pull up resistor control register PUP3 has been made "0".
LCD driver
Because at initial reset, the contents of segment data memory and LC0–LC3 are undefined, there is need
to initialize by software.
Clock timer
(1) When the clock timer has been reset, the interrupt factor flag (IT) may sometimes be set to "1". Conse-
quently, perform flag read (reset the flag) as necessary at reset.
(2) Because the watchdog timer counts up during reset as in the above (1), reset the watchdog timer as
necessary.
(3) When the low-order digits (TM0–TM3) and high-order digits (TM4–TM7) are consecutively read,
proper reading may not be obtained due to the carry from the low-order digits into the high-order
digits (when the reading of the low-order digits and high-order digits span the timing of the carry).
For this reason, perform multiple reading of timer data, make comparisons and use matching data as
result.
Stopwatch timer
When data of the counter is read at run mode, perform the reading after suspending the counter once and
then set SWRUN to "1" again. Moreover, it is required that the suspension period not exceed 976 s (1/4
cycle of 256 Hz).
Programmable timer
(1) When initiating programmable timer count, perform programming by the following steps:
1. Set the initial data to RD0–RD7.
2. Reset the programmable timer by writing "1" to PTRST.
3. Start the down-count by writing "1" to PTRUN.
(2) When the reload register (RD0–RD7) value is set at "00H", the down-counter becomes a 256-value
counter.
(3) When data of the timer is read consecutively in 8 bits in the RUN mode, perform the reading after
suspending the timer once and then set the PTRUN to "1" again. Moreover, it is required that the
suspension period be within 1/4 cycle of the input clock (in case of 1/2 duty). Accordingly, when the
input clock is a fast clock faster than 256 Hz, high speed processing by OSC3 is required.
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