參數(shù)資料
型號： S1C6S460D
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 2 MHz, MICROCONTROLLER, UUC124
封裝： 4.69 X 4.68 MM, DIE-124
文件頁數(shù)： 95/107頁
文件大?。?/td> 788K
代理商： S1C6S460D
80
EPSON
S1C6S460 TECHNICAL MANUAL
CHAPTER 12: SUMMARY OF NOTES
12.2 Summary of Notes by Function
Here, the cautionary notes are summed up by function category. Keep these notes well in mined when
programming.
Memory
Memory is not mounted in unused area within the memory map and in memory area not indicated in
this manual. For this reason, normal operation cannot be assured for programs that have been prepared
with access to these areas.
SVD (Supply voltage detection) circuit
(1) The SVD circuit should normally be turned OFF (SVDON = "0") as the consumption current of the IC
becomes large when it is ON (SVDON = "1").
(2) To obtain a stable detection result, after setting SVDON to "1", provide at least 100 s waiting time
before performing SVDDT reading.
Heavy load protection mode
(1) During heavy load or when 2.2 V or below is detected by SVD, set it to heavy load protection mode.
Unless it is necessary, be careful not to set the heavy load protection mode with the software.
(2) Perform heavy load driving only after setting up at least 1 ms wait time through the software, after
switching to the heavy load protection mode. (See Figure 3.3.2.1.)
(3) When the heavy load protection mode is to canceled after completion of heavy load driving, set up at
least 2 seconds wait time through the software. (See Figure 3.3.2.1.)
Watchdog timer
(1) The watchdog timer must reset within 3-second cycles by the software.
(2) When clock timer resetting (TMRST
← "1") is performed, the watchdog timer is counted up; reset the
watchdog immediately after if necessary.
Oscillation circuit
(1) When high-speed operation of the CPU is not required, observe the following reminders to minimize
power current consumption.
Set the CPU operating clock to OSC1.
Turn the OSC3 oscillation OFF.
Set the internal operating voltage (VS1) to -1.2 V or -2.1 V.
(2) When the CPU is to be operated with OSC1, set the operating voltage to -1.2 V if the power voltage
detected with the SVD circuit were less than 3.1 V (VDD–VSS < 3.1 V); set the operating voltage to -2.1
V if the detected voltage were 3.1 V or more (VDD–VSS
≥ 3.1 V). Moreover, because -1.2 V will be set
during initial reset, be sure to execute the previous process at the beginning of the initial routine.
Note, however, that it can be used fixed at 1.2 V (at OSC1 operation) for power whose initial value is
3.6 V or less as in lithium batteries.
(3) When switching VS1 from -1.2 V (for OSC1 crystal oscillation circuit) to -3.0 V (for OSC3 oscillation
circuit), or vice versa, be sure to hold the -2.1 V setting for more than 5 ms first for power voltage
stabilization.
(VSC1, VSC0) = (0, 0)
→ (0, 1) → 5 ms WAIT → (1, ×)
= (1,
×) → (0, 1) → 5 ms WAIT → (0, 0)
= (0, 0)
→ (1, ×) is prohibited
= (1,
×) → (0, 0) is prohibited
Furthermore, perform the switch after making sure that power voltage by SVD is more than the VS1
(absolute value) set voltage. Switching VS1 when the power source voltage is lower than the set
voltage may cause malfunction.
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