參數(shù)資料
型號(hào)： S1C6S460D
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 2 MHz, MICROCONTROLLER, UUC124
封裝： 4.69 X 4.68 MM, DIE-124
文件頁數(shù)： 77/107頁
文件大小： 788K
代理商： S1C6S460D
S1C6S460 TECHNICAL MANUAL
EPSON
63
CHAPTER 9: SERIAL INTERFACE
(1) Serial data output procedure
The S1C6S460 serial interface is capable of outputting parallel data as serial data, in units of 8 bits.
By setting the parallel data to data registers SD0–SD3 and SD4–SD7 individually and writing "1" to
SCTRG (F7AH [D3]), it synchronizes with the synchronous clock and serial data is output at the
SOUT terminal. The synchronous clock used here is as follows: in the master mode, internal clock
which is output to the SCLK terminal while in the slave mode, external clock which is input from the
SCLK terminal. The serial output of the SOUT terminal changes with the falling edge of the clock that
is input or output from the SCLK terminal.
When the output of the 8 bits data from SD0 to SD7 is completed, the interrupt factor flag ISIO is set
to "1" and interrupt is generated. Moreover, the interrupt can be masked by the interrupt mask
register EISIO. Note, however, that regardless of the setting of the interrupt mask register, the inter-
rupt factor flag is set to "1" after output of the 8 bits data.
(2) Serial data input procedure
The S1C6S460 serial interface is capable of inputting serial data as parallel data, in units of 8 bits.
By writing "1" to SCTRG, the serial data is input from the SIN terminal, synchronizes with the syn-
chronous clock, and is sequentially read in the 8 bits shift register. As in the above item (1), the
synchronous clock used here is as follows: in the master mode, internal clock which is output to the
SCLK terminal while in the slave mode, external clock which is input from the SCLK terminal.
The serial data to the built-in shift register is read with the falling edge of the SCLK signal when SEN
bit is "1" and is read with the rising edge of the SCLK signal when SEN bit is "0". Moreover, the shift
register is sequentially shifted as the data is fetched.
When the input of the 8 bits data from SD0 to SD7 is completed, the interrupt factor flag ISIO is set to
"1" and interrupt is generated. Moreover, the interrupt can be masked by the interrupt mask register
EISIO. Note, however, that regardless of the setting of the interrupt mask register, the interrupt factor
flag is set to "1" after input of the 8 bits data.
Also, the data input in the shift register can be read from data registers SD0–SD7 by software.
(3) Serial data input/output permutation
The S1C6S460 allow the input/output permutation of serial data to be selected by mask option as to
either LSB first or MSB first. The block diagram showing input/output permutation in case of LSB
first and MSB first is provided in Figure 9.4.1.
SD7 SD6 SD5 SD4
Address [F31H]
In case of LSB first
SIN
SOUT
SD3 SD2 SD1 SD0
Address [F30H]
Output
latch
SD0 SD1 SD2 SD3
Address [F30H]
In case of MSB first
SIN
SOUT
SD4 SD5 SD6 SD7
Address [F31H]
Output
latch
Fig. 9.4.1 Serial data input/output permutation
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