參數(shù)資料
型號： S1C6N3B0D0A0100
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, UUC54
封裝： DIE-54
文件頁數(shù)： 7/79頁
文件大?。?/td> 606K
代理商： S1C6N3B0D0A0100
S1C6N3B0 TECHNICAL MANUAL
EPSON
7
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
Table 2.2.1.1 Simultaneous low input time
Oscillation frequency
32.768 kHz (crystal)
65 kHz (CR)
500 kHz (CR, dividing ratio: 1/6)
1 MHz (ceramic, dividing ratio: 1/12)
Model
S1C6N3B0
S1C6A3B0
Simultaneous LOW set-up time (Min.)
3 sec
1.5 sec
1.2 sec
Table 2.2.1.2 Input port combinations
Selection
A
B
C
D
Combination
Not used
K00
K01
K00
K01K02
K00
K01K02K03
When, for instance, mask option D (K00
K01K02K03) is selected, an initial reset is executed when the
signals input to the four ports K00–K03 are all low at the same time. If you use this function, make sure
that the specified ports do not go low at the same time during normal operation.
2.2.2 Reset terminal (RESET)
Initial reset can be executed externally by setting the reset terminal to a low level (VSS). After that the
initial reset is released by setting the reset terminal to a high level (VDD) and the CPU starts operation.
The reset input signal is maintained by the latch and becomes the internal initial reset signal. The latch is
designed to be released by the signal that is divided by the oscillation clock. In normal operation, a reset
release time shown in Table 2.2.2.1 is needed until the internal initial reset is released after the reset
terminal goes to high level. Be sure to maintain the reset terminal at a low level for at least the reset input
time shown in Table 2.2.2.1.
However, when turning the power on, the reset terminal should be set at a low level as in the timing
shown in Figure 2.2.2.1.
Table 2.2.2.1 Reset time
Oscillation frequency
32.768 kHz (crystal)
65 kHz (CR)
500 kHz (CR, division ratio: 1/6)
1 MHz (ceramic, division ratio: 1/12)
Model
S1C6N3B0
S1C6A3B0
Reset input pulse
width (Min.)
5 msec
Reset cancelation time by
hardware inside of IC (Max.)
Reset terminal
→ 250 msec
Reset terminal
→ 125 msec
Reset terminal
→ 98 msec
Reset terminal
→ 98 msec
VDD
RESET
5 msec or more
0.8 V (S1C6N3B0)
1.7 V (S1C6A3B0)
0.5VDD
0.1VDD or less (LOW level)
Power-on
Fig. 2.2.2.1 Initial reset at power on
The reset terminal should be set to 0.1VDD or less (low level) until the supply voltage becomes 0.8 V
(S1C6N3B0) or 1.7 V (S1C6A3B0) or more. After that, a level of 0.5VDD or less should be maintained
more than 5 msec.
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