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參數(shù)資料
| 型號： | S1C6N3B0D0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, UUC54 |
| 封裝： | DIE-54 |
| 文件頁數(shù)： | 46/79頁 |
| 文件大?。?/td> | 606K |
| 代理商： | S1C6N3B0D0A0100 |
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42
EPSON
S1C6N3B0 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIARCUITS AND OPERATION (Stopwatch Timer)
4.8.4 Control of stopwatch timer
Table 4.8.4.1 shows the stopwatch timer control bits and their addresses.
Table 4.8.4.1 I/O memory (Stopwatch timer)
Address
Comment
D3
D2
Register
D1
D0
Name
Init 1
10
0E2H
SWL3
SWL2
SWL1
SWL0
R
SWL3
SWL2
SWL1
SWL0
0
MSB
Stopwatch timer data
1/100sec (BCD)
LSB
0E3H
SWH3
SWH2
SWH1
SWH0
R
SWH3
SWH2
SWH1
SWH0
0
MSB
Stopwatch timer data
1/10sec (BCD)
LSB
0EAH
0
EISW1
EISW0
RR/W
0 3
EISW1
EISW0
– 2
0
–
Enable
–
Mask
Unused
Interrupt mask register (stopwatch 1 Hz)
Interrupt mask register (stopwatch 10 Hz)
0EEH
0
ISW1
ISW0
R
0 3
ISW1 4
ISW0 4
– 2
0
–
Yes
–
No
Unused
Interrupt factor flag (stopwatch 1 Hz)
Interrupt factor flag (stopwatch 10 Hz)
1
2
Initial value at initial reset
Not set in the circuit
3
4
Always "0" being read
Reset (0) immediately after being read
0F9H
0
TMRST SWRUN SWRST
RW
R/W
W
0 3
TMRST3
SWRUN
SWRST3
– 2
Reset
0
Reset
–
Reset
Run
Reset
–
Stop
–
Unused
Clock timer reset
Stopwatch timer Run/Stop
Stopwatch timer reset
SWL0–SWL3: 1/100 sec stopwatch timer (0E2H)
Data (BCD) of the 1/100 sec column of the stopwatch timer can be read. These four bits are read-only, and
cannot be written.
At initial reset, the timer data is set to "0H".
SWH0–SWH3: 1/10 sec stopwatch timer (0E3H)
Data (BCD) of the 1/10 sec column of the stopwatch timer can be read. These four bits are read-only, and
cannot be written.
At initial reset, the timer data is set to "0H".
EISW0, EISW1: Interrupt mask registers (0EAH D0 and D1)
These registers mask the stopwatch timer interrupt.
When "1" is written: Enabled
When "0" is written: Masked
Reading: Valid
The interrupt mask registers (EISW0, EISW1) are used to mask the 10 Hz and 1 Hz interrupts, respec-
tively.
At initial reset, these registers are both set to "0".
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