參數(shù)資料
型號(hào)： S1C60L13F
元件分類(lèi)： 微控制器/微處理器
英文描述： 4-BIT, MROM, 0.032768 MHz, MICROCONTROLLER, PQFP80
封裝： PLASTIC, QFP14-80
文件頁(yè)數(shù)： 42/104頁(yè)
文件大小： 850K
代理商： S1C60L13F
34
EPSON
S1C60N13 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
4.7.4 Data input/output and interrupt function
The serial interface can input/output data via the internal 8 bits shift register. The shift register operates
by synchronizing with either the synchronous clock output from SCLK (P12) terminal (master mode), or
the synchronous clock input to SCLK (P12) (slave mode).
The serial interface generates interrupt on completion of the 8 bits serial data input/output. Detection of
serial data input/output is done by the counting of the synchronous clock (SCLK); the clock completes
input/output operation when 8 counts (equivalent to 8 cycles) have been made and then generates
interrupt.
The serial data input/output procedure data is explained below:
(1) Serial data output procedure and interrupt
The serial interface is capable of outputting parallel data as serial data, in units of 8 bits.
By setting the parallel data to 4 bits registers SD0–SD3 (address 2F0H) and SD4–SD7 (address 2F1H)
individually and writing "1" to SCTRG bit (address 2E7HD3), it synchronizes with the synchronous
clock and serial data is output at the SOUT (P11) terminal. The synchronous clock used here is as
follows: in the master mode, internal clock which is output to the SCLK (P12) terminal while in the
slave mode, external clock which is input from the SCLK (P12) terminal. The serial output of the
SOUT (P11) termina changes with the rising edge of the clock that is input or output from the SCLK
(P12) terminal.
The serial data to the built-in shift register is shifted with the rising edge of the SCLK signal when SE2
bit (address 2F2HD1) is "1" and is shifted with the falling edge of the SCLK signal when SE2 bit
(address 2F2HD1) is "0".
When the output of the 8 bits data from SD0 to SD7 is completed, the interrupt factor flag ISIO
(address 2F3HD0) is set to "1" and interrupt is generated. Moreover, the interrupt can be masked by
the interrupt mask register EISIO (address 2F2HD0).
(2) Serial data input procedure and interrupt
The serial interface is capable of inputting serial data as parallel data, in units of 8 bits.
The serial data is input from the SIN (P10) terminal, synchronizes with the synchronous clock, and is
sequentially read in the 8 bits shift register. As in the above item (1), the synchronous clock used here
is as follows: in the master mode, internal clock which is output to the SCLK (P12) terminal while in
the slave mode, external clock which is input from the SCLK (P12) terminal.
The serial data to the built-in shift register is read with the rising edge of the SCLK signal when SE2
bit is "1" and is read with the falling edge of the SCLK signal when SE2 bit is "0". Moreover, the shift
register is sequentially shifted as the data is fetched.
When the input of the 8 bits data from SD0 to SD7 is completed, the interrupt factor flag ISIO is set to
"1" and interrupt is generated. Moreover, the interrupt can be masked by the interrupt mask register
EISIO. Note, however, that regardless of the setting of the interrupt mask register, the interrupt factor
flag is set to "1" after input of the 8 bits data.
The data input in the shift register can be read from data registers SD0–SD7 by software.
(3) Serial data input/output permutation
The S1C60N13 Series allows the input/output permutation of serial data to be selected by mask
option as to either LSB first or MSB first. The block diagram showing input/output permutation in
case of LSB first and MSB first is provided in Figure 4.7.4.1.
SD7 SD6 SD5 SD4
Address [2F1H]
In case of LSB first
SIN
SOUT
SD3 SD2 SD1 SD0
Address [2F0H]
Output
latch
SD0 SD1 SD2 SD3
Address [2F0H]
In case of MSB first
SIN
SOUT
SD4 SD5 SD6 SD7
Address [2F1H]
Output
latch
Fig. 4.7.4.1 Serial data input/output permutation
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