參數(shù)資料
型號(hào)： S1C60L13F
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 0.032768 MHz, MICROCONTROLLER, PQFP80
封裝： PLASTIC, QFP14-80
文件頁(yè)數(shù)： 14/104頁(yè)
文件大?。?/td> 850K
代理商： S1C60L13F
S1C60N13 TECHNICAL MANUAL
EPSON
9
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
2.2 Initial Reset
To initialize the S1C60N13 Series circuits, initial reset must be executed. There are four ways of doing this.
(1) Initial reset by the power on reset circuit
(2) External initial reset by the RESET terminal
(3) External initial reset by simultaneous high input to terminals K00–K03
(4) Initial reset by the watchdog timer
Figure 2.2.1 shows the configuration of the initial reset circuit.
OSC1
oscillation circuit
Power-on
reset circuit
Time authorize
circuit
OSC1
VSS
Mask option
OSC2
K00
K01
K02
K03
VSS
Initial
reset
RESET
Watchdog
timer
Noise
rejector
Fig. 2.2.1 Configuration of initial reset circuit
2.2.1 Power-on reset circuit
The power-on reset circuit outputs the initial reset signal at power-on until the oscillation circuit starts
oscillating.
Note: The power-on reset circuit may not work properly due to unstable or lower voltage input. The
following two initial reset method are recommended to generate the initial reset signal.
2.2.2 RESET terminal
Initial reset can be executed externally by setting the reset terminal to the high level. This high level must
be maintained for at least 5 msec (when oscillating frequency is fOSC1 = 32 kHz), because the initial reset
circuit contains a noise rejector. When the reset terminal goes low the CPU begins to operate.
2.2.3 Simultaneous high input to input ports (K00–K03)
Another way of executing initial reset externally is to input a high signal simultaneously to the input
ports (K00–K03) selected with the mask option. The specified input port terminals must be kept high for
at least 5 msec (when oscillating frequency is fOSC1 = 32 kHz), because the initial reset circuit contains a
noise rejector. Table 2.2.3.1 shows the combinations of input ports (K00–K03) that can be selected with the
mask option.
Table 2.2.3.1 Input port combination
Selection
A
B
C
D
Combination
Not used
K00
K01
K00
K01K02
K00
K01K02K03
When, for instance, mask option D (K00*K01*K02*K03) is selected, initial reset is executed when the
signals input to the four ports K00–K03 are all high at the same time.
相關(guān)PDF資料
PDF描述
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