參數(shù)資料
型號(hào)： RTL8801
英文描述： Specifications
中文描述： 規(guī)格
文件頁(yè)數(shù)： 9/19頁(yè)
文件大?。?/td> 318K
代理商： RTL8801
RTL8801
Preliminary
PHY register fields map for the cable environment
1999/3
9
Field
size type Power
reset
value
-
description
Physical_ID 6
r
The address of this node determined during self-identification. A
value of 63 indicates a malconfigured bus; the link shall not
transmit any packets.
When set to one, indicate that this node is the root.
Cable Power status.
Root hold-off bit. When set to one, instructs the PHY to attempt
to become the root during the next tree identify process.
Initiate bus reset. When set to one, instructs the PHY to initiate a
bus reset immediately (without arbitration). This bit causes
assertion of the reset state for 166 us and is self-clearing.
Used to configure the arbitration timer setting in order to
optimize gap times according to the topology of the bus. IEEE
1394-1995 4.3.6
constant value of seven, which indiactes extended PHY register
map is implemented
the number of ports implemented by this PHY
Indicates the maximum speed this PHY supports;
000 - 98.304 Mbit/s
001 - 98.304 and 196.608 Mbit/s
010 - 98.304 ,196.60 and 393.216 Mbit/s
011 – Up to786.43 Mbit/s
100 – Up to1,572.864 Mbit/s
101 – Up to 3,145.728 Mbit/s
Worse case repeater delay, expressed as 144+(delay*20)ns.
Link enabled. Default value of one subsequent to a power reset.
Otherwise cleared or set by software to control the value of the
L bit transmitted in the self-ID packet. The transmitted L bit
shall be the logical AND of this bit and the LPS signal.
Contender. Cleared or set by software to control the value of the
C bit transmitted in the self-ID packet.
R
PS
RHB
1
1
1
r
r
rw
-
-
0
IBR
1
rw
0
Gap_count
6
rw
3F
Extended
3
r
7
Total_ports
Max_speed
5
3
r
r
3
010
Delay
Link_active
4
1
r
rw
0
1
Contender
1
rw
Pin
C/LK
ON
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