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參數(shù)資料
| 型號(hào)： | RTL8801 |
| 英文描述： | Specifications |
| 中文描述： | 規(guī)格 |
| 文件頁(yè)數(shù)： | 11/19頁(yè) |
| 文件大小： | 318K |
| 代理商： | RTL8801 |
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RTL8801
Preliminary
1999/3
11
Port_event
1
rw
0
Port event detect. The PHY sets this bit to one if any of
connected, Bias, Disabled or Fault change for a port whose
Int_enable bit is one. The PHY also sets this bit to one if resume
operations commence for any port and Resume_int is one. A
write of one to this bit clears it to zero.
Enable arbitration acceleration. When set to one, the PHY shall
use the enhancements specification in P1394A.
Enable multi-speed packet concatenation. When set to one, the
Link shall signal the speed of all packets to the PHY.
Selects which of eight possible PHY register pages are
accessible through the window at PHY register address 1000b
through 1111b, inclusive.
0000 If the page selected by Page_select presents per port
information, this field selects which port’s registers are
accessible through the window at PHY register addressed 1000b
through 1111b, inclusive.
Enab_accel
1
rw
0
Enab_multi
1
rw
0
Page_select
3
rw
000
Port_select
4
rw
7.2.PHY register page0: Port Status page
The port Status page is used to access configuration and status information for each of the PHY’s
port. The port is selected by writing zero to Page_select and the desired port number to Port_select
in the PHY register at address 0111.
0
1
2
3
4
5
6
7
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
AStat
Negotiated_speed
Y
￡
Y
￡
Y
￡
Y
￡
Y
￡
Y
￡
BStat
Int_enable Fault
Y
￡
Y
Y
￡
Y
Y
￡
Y
Y
￡
Y
Y
￡
Y
Y
￡
Y
Child connected
Bias
￡
￡
￡
￡
￡
￡
￡
Disabled
￡
￡
￡
￡
￡
￡
￡
￡
￡
￡
￡
￡
￡
￡
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
￡
￡
￡
￡
￡
￡
Y
Y
Y
Y
Y
Y
￡
￡
￡
￡
￡
￡
￡
￡
￡
￡
￡
￡
Y
Y
Y
Y
Y
Y
Note:
￡
YReserved
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