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參數(shù)資料
| 型號： | RTL8801 |
| 英文描述： | Specifications |
| 中文描述： | 規(guī)格 |
| 文件頁數(shù)： | 12/19頁 |
| 文件大?。?/td> | 318K |
| 代理商： | RTL8801 |
RTL8801
Preliminary
1999/3
12
PHY register port status page fields
Field
Size Type Power
reset
value
-
Description
Astat
2
r
TPA line State for the port
00 = invalid
01 =1
10 =0
11 =z
(same encoding as Astat)
If equal to one, the port is a child, else a parent. The
meaning of this bit is undefined from the time a bus reset is
detected until the PHY transitions to state T1:Child
Handshake during the tree identify process(see 4.4.2.2 in
IEEE Std 1394-1995)
If equal to one, the port is connected, else disconnected.
The value reported by this bit is filtered by hysteresis logic
to reduce multiple status changes caused by contact scrape
when a connector is inserted or removed.
If equal to one, bias voltage is detected( possible
connection). The value reported by this bit is filtered by
hysteresis logic to reduce multiple status changes caused
by contact scrape when a connector is inserted or removed.
When set to one, the port shall be disabled. The value of
this
bit
subsequent
to
implementation-dependent, but should be a strappable
option.
Indicated the maximum speed negotiated between this
PHY port and its immediately connected port; the encoding
is
000 – 98.304Mbit/s
001 - 196.608 Mbit/s
010 - 393.216 Mbit/s
Bstat
Child
2
1
r
r
-
-
Connected
1
r
0
Bias
1
r
-
Disabled
1
rw 0
a
power
reset
is
Negotiated_
speed
3
r
-
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