參數(shù)資料
型號: RTL8801
英文描述: Specifications
中文描述: 規(guī)格
文件頁數(shù): 5/19頁
文件大?。?/td> 318K
代理商: RTL8801
RTL8801
Preliminary
1999/3
5
TPBIAS1
TPBIAS2
TPBIAS3
O
37, 42, 48
Portn, twisted pair bias. It provides the 1.86-V nominal bias voltage
needed for proper operation of the twisted-pair cable drivers and
receivers and for sending a valid cable connection signal to the remote
nodes.
Power class indicators. The PC signals set the bit values of the three
power-class bits in the Self-ID packet (bit 21, 22 and 23). These bits
can be programmed by tying the terminals to VDD or to GND.
Crystal oscillator. XI and XO connect to a 24.576 MHz parallel
resonant fundamental mode crystal
PLL circuit ground. These pins should be tied together to the low
impedance ground plane
PLL circuit power. PLLVDD supplies power to the PLL circuit
Analog power. AVDD supplies power to the analog port of the device
PC0-PC2
I
20, 21, 22
XI
XO
PLLGND
-
59, 60
-
52, 56
PLLVDD
AVDD
-
-
51
30,31,43,50.
AVSS
-
32,49,53,54 Analog ground. These pins should be tied together to the low
impedance ground plane
55
Current Setting Resistor input. This pin is connected to an external
resistor to set the internal operating current and cable driver output
current
19
Port configuration monitor input. The pin is only active in power on
stage and meets the requirement of Open HCI.
7,17,26,57,
62
2,14, 25,29,
58,64
impedance ground plane
61
Reset. An external capacitor in parallel with a resistor are required for
proper power-up operation
28
Test control input. This pin is used in the manufacturing test of the
device. For normal use it should be tied to DVSS.
27
Test control input. This pin is used in the manufacturing test of the
device. For normal use it should be tied to DVDD.
BTSET
I
PDISABLE
I
DVDD
-
Digital power. DVDD supplies power to the digital port of the device
DVSS
-
Digital Ground. These pins should be tied together to the low
RESET\
I
TEST1
I
TEST2
I
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