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參數(shù)資料
| 型號： | RTL8204 |
| 英文描述： | Layout reference |
| 中文描述： | 布局參考 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大?。?/td> | 73K |
| 代理商： | RTL8204 |
8201layoutguide(V1.00)
2000-11-08
REALTEK
Chip design & System design
5
MAC. When link at 10M speed, the TXCLK and RXCLK is 2.5 MHz clock to
MAC. Both TXData and Rxdata are latched at rising edge of clock. The detail MII
timing description and specification can refer to IEEE802.3u clause 22.
5. Power and Ground Plane
!
3.3V
power: support RTL8201 and other devices. Avoid using unnecessary power
trace to RTL8201 and
keep these traces as short and wide and make good use of via.
Keep the 3.3V power plane as a whole, and leave some space for Analog power
plane.
CNR or ACR connector
Analog power
RTL8201
Digital VDD power
RTL8201
VDD
VDD
VDD
VDD
VDD
!
As showed in RTL8201 schematic, we have reserved a region “Block A”, please
reserve the components space and pads in your layout for future 2.5v core
extension.
!
GND plane
We can separate the digital GND to Analog GND as follow:
Partition of GND plane need experience and experiment, the key point is to keep
analog GND's return path about equal to the common GND, if you do not have
confidence on this, simply leave the GND plane unchanged, ie, no partition at all.
!
For all partition on Power/GND plane, no right angle is recommend. The same to
the signal/power/bus traces.
!
Digital GND's of RTL8201 should use via from digital GND plane to device's pin
and Analog GND's of RTL8201 and Tx
±
/Rx
±
peripheral circuit GND's should
LAN
Controller
C
RTL8201
(optional)
A
B
Dimension A = 1 to 7 inch
Dimension B = 1 to 3 inch
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