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| 型號： | RTL8201CP-VD-LF |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SINGLE-CHIP/SINGLE-PORT 10/100M FAST ETHERNET PHYCEIVER (With Auto Crossover) |
| 中文描述： | SINGLE-CHIP/SINGLE-PORT個10/100M快速以太網PHYCEIVER（自動交叉） |
| 文件頁數(shù)： | 9/38頁 |
| 文件大小： | 512K |
| 代理商： | RTL8201CP-VD-LF |
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RTL8201CP
Datasheet
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
4
Track ID: JATR-1076-21 Rev. 1.21
5. Pin Description
LI: Latched Input during Power up or Reset
O: Output
I: Input
IO: Bi-directional input and output
P: Power
5.1. MII Interface
Table 1. MII Interface
Description
Transmit Clock.
This pin provides a continuous clock as a timing reference for TXD[3:0] and
TXEN.
Transmit Enable.
The input signal indicates the presence of valid nibble data on TXD[3:0].
Transmit Data.
The MAC will source TXD[0..3] synchronous with TXC when TXEN is
asserted.
Receive Clock.
This pin provides a continuous clock reference for RXDV and RXD[0..3]
signals. RXC is 25MHz in 100Mbps mode and 2.5Mhz in 10Mbps mode.
Collision Detect.
COL is asserted high when a collision is detected on the media.
During power on reset, this pin status is latched to determine at which LED
mode to operate:
0
:
CP LED mode
1
:
BL LED mode
An internal weak pull low resistor sets this to the default CP LED mode. It is possible
to use an external 5.1K
pull high resistor to enable BL LED mode.
Carrier Sense.
This pin’s signal is asserted high if the media is not in Idle state.
An internal weak pull low resistor sets this to normal operation mode. An external
5.1K
pull low resistor could be reserved to ensure operating at normal mode.
Receive Data Valid.
This pin’s signal is asserted high when received data is present on the RXD[3:0]
lines. The signal is de-asserted at the end of the packet. The signal is valid on
the rising edge of the RXC.
Receive Data.
These are the four parallel receive data lines aligned on the nibble boundaries
driven synchronously to the RXC for reception by the external physical unit
(PHY).
Receive Error.
If a 5B decode error occurs, such as invalid /J/K/, invalid /T/R/, or invalid
symbol, this pin will go high.
Fiber/UTP Enable.
During power on reset, this pin status is latched to determine the media mode to
operate in.
1: Fiber mode
0: UTP mode
An internal weak pull low resistor sets this to the default of UTP mode. It is possible to
use an external 5.1K
pull high resistor to enable fiber mode.
After power on, the pin operates as the Receive Error pin.
Name
TXC
Type
O
Pin No.
7
TXEN
I
2
TXD[3:0]
I
3, 4, 5, 6
RXC
O
16
COL
LI/O
1
CRS
LI/O
23
RXDV
O
22
RXD[3:0]
O
18, 19, 20, 21
RXER/
FXEN
LI/O
24
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