參數(shù)資料
型號(hào)： RTL8201CP-VD-LF
廠商： Electronic Theatre Controls, Inc.
英文描述： SINGLE-CHIP/SINGLE-PORT 10/100M FAST ETHERNET PHYCEIVER (With Auto Crossover)
中文描述： SINGLE-CHIP/SINGLE-PORT個(gè)10/100M快速以太網(wǎng)PHYCEIVER（自動(dòng)交叉）
文件頁(yè)數(shù)： 17/38頁(yè)
文件大小： 512K
代理商： RTL8201CP-VD-LF
RTL8201CP
Datasheet
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
12
Track ID: JATR-1076-21 Rev. 1.21
6.8. Register 16 NWay Setup Register (NSR)
Table 16. Register 16 NWay Setup Register (NSR)
Description
1: LED4 Pin indicates linkpulse
1: Auto-negotiation speeds up internal timer
1: Set NWay to loopback mode
1: Auto-negotiation experienced ability detect state
1: Auto-negotiation experienced parallel detection fault state
1: Auto-negotiation experienced link status check state
Address
16:15~12
16:11
16:10
16:9
16:8~3
16:2
16:1
16:0
Name
Reserved
ENNWLE
Testfun
NWLPBK
Reserved
FLAGABD
FLAGPDF
FLAGLSC
Mode
RW
RW
RW
RO
RO
RO
Default
0
0
0
0
0
0
6.9. Register 17 Loopback, Bypass, Receiver Error Mask
Register (LBREMR)
Table 17. Register 17 Loopback, Bypass, Receiver Error Mask Register (LBREMR)
Name
Description
RPTR
Set to 1 to put the RTL8201CP into repeater mode.
BP_4B5B
Assertion of this bit allows bypassing of the 4B/5B & 5B/4B
encoder.
BP_SCR
Assertion of this bit allows bypassing of the
scrambler/descrambler.
LDPS
Set to 1 to enable Link Down Power Saving mode.
AnalogOFF
Set to 1 to power down analog function of transmitter and receiver.
Reserve
Reserved.
LB
Set to 1 to enable DSP Loopback.
F_Link_10
Used to logic force good link in 10Mbps for diagnostic purposes.
F_Link_100
Used to logic force good link in 100Mbps for diagnostic purposes.
JBEN
Set to 1 to enable Jabber Function in 10Base-T.
CODE_err
Assertion of this bit causes a code error detection to be reported.
PME_err
Assertion of this bit causes a pre-mature end error detection to be
reported.
LINK_err
Assertion of this bit causes a link error detection to be reported.
PKT_err
Assertion of this bit causes a ‘detection of packet errors due to
722 ms time-out’ to be reported.
FXMODE
This bit indicates whether Fiber Mode is Enabled.
RMIIMODE
This bit indicates whether RMII mode is Enabled.
Address
17:15
17:14
Mode
RW
RW
Default
0
0
17:13
RW
0
17:12
17:11
17:10
17:9
17:8
17:7
17:6
17:5
17:4
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
1
1
0
1
0
17:3
17:2
RW
RW
0
0
17:1
17:0
RO
RO
0
0
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