參數(shù)資料
型號(hào)： RTL8201CP-VD-LF
廠商： Electronic Theatre Controls, Inc.
英文描述： SINGLE-CHIP/SINGLE-PORT 10/100M FAST ETHERNET PHYCEIVER (With Auto Crossover)
中文描述： SINGLE-CHIP/SINGLE-PORT個(gè)10/100M快速以太網(wǎng)PHYCEIVER（自動(dòng)交叉）
文件頁(yè)數(shù)： 11/38頁(yè)
文件大小： 512K
代理商： RTL8201CP-VD-LF
RTL8201CP
Datasheet
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
6
Track ID: JATR-1076-21 Rev. 1.21
5.5. Device Configuration Interface
Table 5. Device Configuration Interface
Description
Set high to isolate the RTL8201CP from the MAC. This will also isolate the MDC/MDIO
management interface. In this mode, the power consumption is minimum. This pin can be
directly connected to GND or VCC.
Set high to put the RTL8201CP into repeater mode. This pin can be directly connected
to GND or VCC.
This pin is latched to input during a power on or reset condition. Set high to put
the RTL8201CP into 100Mbps operation. This pin can be directly connected to GND or
VCC.
This pin is latched to input during a power on or reset condition. Set high to
enable full duplex. This pin can be directly connected to GND or VCC.
This pin is latched to input during a power on or reset condition. Set high to
enable Auto-negotiation mode, set low to force mode. This pin can be directly
connected to GND or VCC.
Set high to put the RTL8201CP into LDPS mode. This pin can be directly connected
to GND or VCC. See 7.7 Power Down, Link Down, Power Saving, and Isolation
Modes, page 20, for more information.
This pin is latched to input during a power on or reset condition. Pull high to set
the RTL8201CP into MII mode operation. Set low for SNI mode. This pin can be
directly connected to GND or VCC.
Name
ISOLATE
Type
I
Pin No.
43
RPTR
I
40
SPEED
LI
39
DUPLEX
LI
38
ANE
LI
37
LDPS
I
41
MII/SNIB
LI/O
44
5.6. LED Interface/PHY Address Configuration
These five pins are latched into the RTL8201CP during power up reset to configure the PHY address
[0:4] used for the MII management register interface. In normal operation, after initial reset, they are used
as driving pins for status indicator LEDs. The driving polarity, active low or active high, is determined by
each latched status of the PHY address [4:0] during power-up reset. If the latched status is High, then it
will be active low. If the latched status is Low, then it will be active high. See section 7.5 LED and PHY
Address Configuration, page 19, for more information.
Table 6. LED Interface/PHY Address Configuration
Pin No.
Description
9
PHY Address [0].
Link LED.
Lit when linked.
10
PHY Address [1].
Full Duplex LED.
Lit when in Full Duplex operation.
12
PHY Address [2].
CP LED Mode: 10 ACT LED
Blinking when transmitting or receiving data.
BL LED Mode: Link 10 / ACT LED
Active when linked in 10Base-T mode, and blinking when transmitting or
receiving data.
Name
PHYAD0/
LED0
Type
LI/O
PHYAD1/
LED1
LI/O
PHYAD2/
LED2
LI/O
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RTL8201CP電路圖-3 制造商:未知廠家 制造商全稱:未知廠家 功能描述:RTL8201CP電路圖-3
RTL8201EL 制造商:Realtek Semiconductor 功能描述:IC,LAN TRANSCEIVER,SINGLE,CMOS,QFP,48PIN,PLASTIC
RTL8201F 制造商:Realtek 功能描述:10/100 PHY recevier
RTL8201L 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Layout guide
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