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參數(shù)資料
| 型號： | RJ80530VY700256 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 78/89頁 |
| 文件大?。?/td> | 1672K |
| 代理商： | RJ80530VY700256 |
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Mobile Intel
Pentium
III Processor-M Datasheet
78
Datasheet
298340-002
Table 44. BSEL[1:0] Encoding
BSEL[1:0]
System Bus Frequency
01
100 MHz
11
133 MHz
CLKREF (Analog)
The CLKREF (System Bus Clock Reference) signal provides a reference voltage to define the trip
point for the BCLK signal on platforms supporting Single Ended Clocking. This signal should be
connected to a resistor divider to generate 1.25V from the 2.5-V supply. A minimum of 1-uF
decoupling capacitance is recommended on CLKREF. On systems with Differential Clocking, the
CLKREF pin functions as the BCLK# input.
CMOSREF (Analog)
The CMOSREF (CMOS Reference Voltage) signal provides a DC level reference voltage for the
CMOS input buffers. CMOSREF must be generated from a stable 1.5-V supply and must meet the
V
CMOSREF
specification. The same 1.5-V supply should be used to power the chipset CMOS I/O
buffers that drive the CMOS signals. Please refer to the platform design guidelines for resistor divider
recommendations.
D[63:0]# (I/O - AGTL)
The D[63:0]# (Data) signals are the data signals. These signals provide a 64-bit data path between both
system bus agents, and must be connected to the appropriate pins/balls on both agents. The data driver
asserts DRDY# to indicate a valid data transfer.
DBSY# (I/O - AGTL)
The DBSY# (Data Bus Busy) signal is asserted by the agent responsible for driving data on the system
bus to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This
signal must be connected to the appropriate pins/balls on both agents on the system bus.
DEFER# (I - AGTL)
The DEFER# (Defer) signal is asserted by an agent to indicate that the transaction cannot be
guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the addressed
memory agent or I/O agent. This signal must be connected to the appropriate pins/balls on both agents
on the system bus.
DEP[7:0]# (I/O - AGTL)
The DEP[7:0]# (Data Bus ECC Protection) signals provide optional ECC protection for the data bus.
They are driven by the agent responsible for driving D[63:0]#, and must be connected to the
appropriate pins/balls on both agents on the system bus if they are used. During power-on
configuration, DEP[7:0]# signals can be enabled for ECC checking or disabled for no checking.
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