參數(shù)資料
型號： RJ80530VY700256
英文描述： Microprocessor
中文描述： 微處理器
文件頁數(shù)： 20/89頁
文件大?。?/td> 1672K
代理商： RJ80530VY700256
Mobile Intel
Pentium
III Processor-M Datasheet
20
Datasheet
298340-002
Table 6. Recommended Resistors for Mobile Intel Pentium III Processor-M Signals
Recommended
Resistor Value (
)
Mobile Intel Pentium III Processor-M Signal
1, 2
No pull-up
GHI#
3
BREQ0#
4
10 pull-down
14 pull-up
NCTRL
39 pull-up
TMS
39 pull-down
TCK
PRDY#, RESET#
5
56.2 pull-up
56.2 pull-down
RTTIMPEDP
110 pull-down
EDGECTRLP
150 pull-up
PICD[1:0], TDO
200-300 pull-up
PREQ#, TDI
500 pull-down
TRST#
1K pull-up
BSEL[1:0], TESTHI, VID[4:0], VTTPWRGD
1K pull-down
TESTLO
1.5k pull-up
FERR#, IERR#, PWRGOOD
3K pull-up
FLUSH#
Additional Pullup/Pulldown Resistor Recommendations
7
270 pull-up
SMI#
680 pull-up
STPCLK#
1.5k pull-up
NOTES:
1.
The recommendations above are only for signals that are being used. These recommendations are maximum
values only; stronger pull-ups may be used. Pull-ups for the signals driven by the chipset should not violate the
chipset specification. Refer to Section 3.1.4 for the required pull-up or pull-down resistors for signals that are not
being used.
2.
Open-drain signals must never violate the undershoot specification in Section 4.3. Use stronger pull-ups if there
is too much undershoot.
3.
GHI# has an on-die pull-up to V
CCT
.
4.
A pull-down on BREQ0# is an alternative to having the central agent to drive BREQ0# low at reset.
5.
A 56.2
1% terminating resistor connected to V
CCT
is required.
6.
The following signals are actively driven high by the ICH3-M component and do not need external pull up
resistors on ICH3-M based platforms: A20M#, DPSLP#, INIT#, IGNNE#, LINT0/INTR, LINT1/NMI, SMI#,
STPCLK#.
7.
These pull up recommendations apply to systems on which these signals are not actively pulled high such as
those utilizing the 82443MX chipset.
A20M#, DPSLP#, INIT#, IGNNE#, LINT0/INTR, LINT1/NMI
3.1.1
Power Sequencing Requirements
Unlike the mobile Pentium
III
processor, the Mobile Intel Pentium
III
Processor-M does have specific
power sequencing requirements. The power on sequencing and timings are shown in Figure 12 and
Table 25. Power down timing requirements are shown in Figure 13, Figure 14, and Table 25. The V
CC
power plane must not rise too fast. At least 200
μ
sec (T
R
) must pass from the time that V
CC
is at 10%
of its nominal value until the time that V
CC
is at 90% of its nominal value. The recommended V
CC
rise
and fall times for Enhanced Intel SpeedStep technology and Deeper Sleep transitions are 100
μ
sec
(max). For more details on Intel
Mobile Voltage Positioning -II (IMVP-II) implementation, please
contact your Intel Field Sales Representative.
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