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| 型號： | RJ80530VY700256 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 36/89頁 |
| 文件大小： | 1672K |
| 代理商： | RJ80530VY700256 |
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Mobile Intel
Pentium
III Processor-M Datasheet
36
Datasheet
298340-002
Table 20. System Bus Clock AC Specifications (133 MHz, Single Ended)
1
Symbol
Parameter
Min
Max
Unit
Figure
Notes
System Bus Frequency
133
MHz
T1S
BCLK Period
7.5
7.65
ns
6
Note 2
T1Sabs
BCLK Period – Instantaneous
Minimum
7.25
Note 2
T2S
BCLK Period Stability
±250
ps
Notes 2, 3, 4
T3S
BCLK High Time
1.4
ns
6
at>2.0V
T4S
BCLK Low Time
1.4
ns
6
at<0.5V
T5S
BCLK Rise Time
0.4
1.6
ns
6
Note 5
T6S
NOTES:
1.
All AC timings for GTL+ and CMOS signals are referenced to the BCLK rising edge at 1.25V.
2.
Period, jitter, skew and offset measured at 1.25V.
3.
Not 100% tested. Specified by design/characterization.
4.
Measured on the rising edge of adjacent BCLKs at 1.25V. The jitter present must be accounted for as a
component of BCLK skew between devices.
5.
Measured between 0.5V and 2.0V.
BCLK Fall Time
0.4
1.6
ns
6
Note 5
Table 21. System Bus Clock AC Specifications (100 MHz, Single Ended)
1
Symbol
Parameter
Min
Typ
Max
Unit
Figure
Notes
System Bus Frequency
100
MHz
T1S1
BCLK Period
10
ns
6
Note 2
T1S1abs BCLK Period – Instantaneous
Minimum
9.75
ns
Note 2
T2S1
BCLK Period Stability
±250
ps
Notes 2, 3, 4
T3S1
BCLK High Time
2.70
ns
6
at>2.0V
T4S1
BCLK Low Time
2.45
ns
6
at<0.5V
T5S1
BCLK Rise Time
0.4
1.6
ns
6
Note 5
T6S1
NOTES:
1.
All AC timings for AGTL and CMOS signals are referenced to the BCLK rising edge at 1.25V.
2.
Period, jitter, skew and offset measured at 1.25V.
3.
Not 100% tested. Specified by design/characterization.
4.
Measured on the rising edge of adjacent BCLKs at 1.25V. The jitter present must be accounted for as a
component of BCLK skew between devices.
5.
Measured between 0.5V and 2.0V.
BCLK Fall Time
0.4
1.6
ns
6
Note 5
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