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| 型號： | RJ80530VY700256 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 34/89頁 |
| 文件大?。?/td> | 1672K |
| 代理商： | RJ80530VY700256 |
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Mobile Intel
Pentium
III Processor-M Datasheet
34
Datasheet
298340-002
Table 18. CLKREF, APIC, TAP, CMOS, and Open-drain Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes
V
IL15
Input Low Voltage, 1.5V CMOS
–0.15
V
– 300 mV
V
V
IL18
Input Low Voltage, 1.8V CMOS
–0.36
0.36
V
Notes 1, 2
V
IH15
Input High Voltage, 1.5V CMOS
V
CMOSREFmax
+
250 mV
2.0
V
Note 11
V
IH15PICD
Input High Voltage, 1.5V PICD[1:0]
V
+
200 mV
2.0
V
Note 12
V
IH18
Input High Voltage, 1.8V CMOS
1.44
2.0
V
Notes 1, 2
V
OH15
Output High Voltage, 1.5V CMOS
N/A
1.615
V
All outputs are Open-drain
V
OH33
Output High Voltage, 3.3V signals
2.0
3.465
V
3.3V + 5%
V
OL33
Output Low Voltage, 3.3V signals
0.8
V
V
OL
Output Low Voltage
0.3
V
Note 9
V
CMOSREF
CMOSREF Voltage
0.90
1.10
V
Note 4
V
CLKREF
CLKREF Voltage
1.187
1.312
V
Note 10
V
ILVTTPWR
Input Low Voltage, VTTPWRGD
0.4
V
Note 7
V
IHVTTPWR
Input High Voltage, VTTPWRGD
1.0
V
Note 7
V
ILGHI
Input Low Voltage, GHI#
0.2
V
Note 8
V
IHGHI
Input High Voltage, GHI#
1.0
V
Note 8
R
ON
30
mA
Note 3
I
OL
Output Low Current
10
Note 6
I
L
Leakage Current for Inputs, Outputs
and I/Os
±100
μ
A
Note 5
NOTES:
1.
Parameter applies to the PWRGOOD signal only.
2.
V
and V
only apply when BCLK, BCLK# and PICCLK are stopped. PICCLK should be stopped in the
low state. See Table 30 and Table 31 for DC levels when BCLK and BCLK# are stopped.
3.
Measured at 9 mA.
4.
V
should be created from a stable 1.5V supply using a voltage divider. It must track the voltage supply
to maintain noise immunity. The same 1.5V supply should be used to power the chipset CMOS I/O buffers that
drive these signals.
5.
(0
≤
VIN/OUT
≤
V
IHx,max
).
6.
Specified as the minimum amount of current that the output buffer must be able to sink. However, V
OL,max
cannot
be guaranteed if this specification is exceeded.
7.
Parameter applies to VTTPWRGD signal only.
8.
Parameter applies to GHI# signal only.
9.
Applies to non-AGTL signals except BCLK, PWRGOOD, PICCLK, BSEL[1:0], VID[4:0].
10. ±5% DC tolerance. CLKREF must be generated from the same 2.5V supply used to generate the BCLK signal.
AC Tolerance must be less than -40dB at 1 MHz. The CLKREF DC spec only applies to platforms supporting
single-ended clocking.
11. Applies to all TAP and CMOS signals (not to APIC signals).
12. Applies to PICD[1:0].
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